Cesar0182
Member level 5
Greetings ... tell you that a few days ago I translated a single verilog file to vhdl to add it to my vhdl project in Vivado 2017.3 which has the function of controlling the transmission and reception of data for a hotlink interface, apparently no problem in simulation , synthesis and implementation through a tcl scritp, but when testing it in the hardware I observe that the transmission speed dramatically reduces. I was suggested to analyze the design of the project implemented in the device and in this way verify that the design had changed with respect to a version that still used the verilog file, as shown in the attached image.
The truth is that I am new to the area of implementation and would like to know how I can make use of the resources of only certain regions of the device?
The truth is that I am new to the area of implementation and would like to know how I can make use of the resources of only certain regions of the device?