firasgany7
Junior Member level 1
Hello guys,
i'm trying to understand the output of my phase detector only for a pulse that goes from zero to one.
i'm trying to substitute the clocks initial values into the circuit and try to calculate the output, but since we have SR latches in this example that i'm showing, what should be the other values and what is the assumption?
why this circuit can't go to meta-stability state?
Note: all the gates are transistor level and not idea.
these are the schematics and the value that I substituted and the simulation:
as you see, the up starts with 0.7 volts, and I don't know how to explain that.
thanks in advance for any kind of help.
i'm trying to understand the output of my phase detector only for a pulse that goes from zero to one.
i'm trying to substitute the clocks initial values into the circuit and try to calculate the output, but since we have SR latches in this example that i'm showing, what should be the other values and what is the assumption?
why this circuit can't go to meta-stability state?
Note: all the gates are transistor level and not idea.
these are the schematics and the value that I substituted and the simulation:
as you see, the up starts with 0.7 volts, and I don't know how to explain that.
thanks in advance for any kind of help.