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by writing a VHDL package file and then including it using the following line at the top of the file (along with the ieee libararies)Could you please explain how I include this .h file to my code through a package or library?
Code VHDL - [expand] 1 2 --assuming it my_package.vhd is compiled to the work library use work.my_package.all;
IMO, if someone is using an initial block in synthesizable code then I would suspect the code to be less than quality code (i.e. it's probably garbage).Okay, if there is no other way, I will start translating my .h file to vhdl.
Another question I have is the use of "initial begin" in verilog. Is there any equivalent in vhdl for this?