dpaul
Advanced Member level 5
I am using Xilinx Vivado 2018.3.
I tried to use the synthesis directives 'synthesis translate_off/on' within a VHDL 2008 package definition.
The xsim compiler gave me errors for that. Are the directives not supported at that place?
I have consulted UG901, Chapter2, and there it is only mentioned that "This attribute can only be set in the RTL." In my opinion the package definition part is also a valid RTL region.
Or is this problem Xilinx specific?
Any info on how other synth tools behave when these directives are used within a VHDL 2008 package definition?
I tried to use the synthesis directives 'synthesis translate_off/on' within a VHDL 2008 package definition.
The xsim compiler gave me errors for that. Are the directives not supported at that place?
I have consulted UG901, Chapter2, and there it is only mentioned that "This attribute can only be set in the RTL." In my opinion the package definition part is also a valid RTL region.
Or is this problem Xilinx specific?
Any info on how other synth tools behave when these directives are used within a VHDL 2008 package definition?