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  1. #1
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    Inverters as Level Shifter with HVT and LVT transistors

    Hi All,

    In my design I need to shift a 0.4V signal clock to a 1.2V signal clock, the clock is a ring osc with a 0v4 supply.

    I implemented two inverters in cascade as level shifters, with the first stage inverter having an HVT pmos and an LVT nmos, while the second stage are just normal pmos and nmos. It seems to work and copies the clock signal with just a higher level.

    I would just like to ask, what problems could this have over the typical latched level shifter? It seems to work fine, but I am not very familiar with level shifters.

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  2. #2
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    Re: Inverters as Level Shifter with HVT and LVT transistors

    Static power consumption when input is high.
    When your input is high, there is a |Vgs| = 0.8V which will cause leakage current to flow. When your input is 0, the NMOS is turned off and there is no leakage.



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  3. #3
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    Re: Inverters as Level Shifter with HVT and LVT transistors

    isnt that the same with the normal operation of the inverter?

    How does this compare with a latched level shifter?



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  4. #4
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    Re: Inverters as Level Shifter with HVT and LVT transistors

    A CMOS inverter has no static power consumption. When input is high, the Vsg across PMOS = 0; no PMOS drain current. When input is low, Vgs across NMOS =0 ; no NMOS drain current.
    In your case, there will be a continuous current draw until your outputs reach the supply rails. (its not really "static" though). Level shifters employ a cross coupled pair that ensures the output clams to the supply using positive feedback.
    AC coupled level shifters will be a better choice for your application.



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