sqx
Member level 1
Hi,
For CMOS integrated LNA in this picture, is LD a part of the matching network?
Usually if LD and C1 is a bias Tee, LD should be a RF choke and C1 should be a DC blocking cap. But such large L and C can't be built on chip. So I assume they are just matching network. But why do we sometimes need a bias Tee? If LD is not large, will the amp be affected if VDD is not an ideal voltage source?
For CMOS integrated LNA in this picture, is LD a part of the matching network?
Usually if LD and C1 is a bias Tee, LD should be a RF choke and C1 should be a DC blocking cap. But such large L and C can't be built on chip. So I assume they are just matching network. But why do we sometimes need a bias Tee? If LD is not large, will the amp be affected if VDD is not an ideal voltage source?