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    Is FET operating withinin SOA?...Pulsed linear regulator

    Hello,
    We have the following waveform in the STD1NK80Z FET (DPAK). It recurs every 10ms as shown.
    We need to know if this violates the SOA.
    To me, these pulses equate to repetitive pulses of [45V and 430mA and 650us long].
    How from the datasheet can we tell that this is acceptable?
    The SOA graph on page 4 shows what’s acceptable for a “single pulse”……..but how are we supposed to know what’s ok for our pulse train?
    Also, the SOA graph on page 4 says “Tj=150degC and Tc = 25degC”..
    What does this mean?......surely it’s the junction temperature, Tj, that is the significant parameter, so why do they bother to specify that the case temperature, Tc, is at 25degc?

    STD1NK80Z datasheet:
    https://www.st.com/resource/en/datasheet/CD00058073.pdf

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    Re: Is FET operating withinin SOA?...Pulsed linear regulator

    Quote Originally Posted by treez View Post
    Hello,
    We have the following waveform in the STD1NK80Z FET (DPAK). It recurs every 10ms as shown.

    or is it 7.6ms ??

    We need to know if this violates the SOA.

    To me, these pulses equate to repetitive pulses of [45V and 430mA and 650us long].

    SO what is the power and duty cycle, d ?

    How from the datasheet can we tell that this is acceptable?

    Did you ever take Calculus and graphical integration?


    The SOA graph on page 4 shows what’s acceptable for a “single pulse”……..but how are we supposed to know what’s ok for our pulse train?
    Also, the SOA graph on page 4 says “Tj=150degC and Tc = 25degC”..
    What does this mean?......surely it’s the junction temperature, Tj, that is the significant parameter, so why do they bother to specify that the case temperature, Tc, is at 25degc?
    Because the thermal rise is determined by repetitive power and thermal resistance using an infinite case heatsink to isolate 1 thermal variable Tjc.. Of course, if case rises, so does junction by the same.

    Click image for larger version. 

Name:	FET T rise.jpg 
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ID:	154822


    STD1NK80Z datasheet:
    https://www.st.com/resource/en/datasheet/CD00058073.pdf
    Thus you need both SOA to ensure you are well below limit (OK) then use Thermal IMpedance and compute T rise from integrated product of of VI=P_rms * d duty cycle


    I see an average <1 deg C rise due to this data.

    8% duty of 19W (VI_rms) pulse = 1.5W @ 20% thermal impedance =K



    - - - Updated - - -

    EDIT:

    I see ~ 24W peak @ 400us with a SOA max just over 100W so you have about 76W SOA margin due to thermal shock

    Your temp rise due to the pulse rise would be ~ 1 deg'C so not much thermal shock where I used the single pulse to estimate junction rise during pulse
    Click image for larger version. 

Name:	SOA FET.jpg 
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Size:	170.6 KB 
ID:	154824

    but repetitive rise is based on duty cycle of 8% duty of 19W =1.5W * (Rjc=2.78'C/W) = 4.x deg C rise above case
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    A better question deserves a better answer. ™
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    Re: Is FET operating withinin SOA?...Pulsed linear regulator

    “Tj=150degC and Tc = 25degC”
    maximum dissipation is obtained by holding the tab at 25degC with the junction at 150 degC - the heatflow is then maximum - a lot of SOA curves are published on the basis of the tab being connected to an infinite heatsink at 25degC

    The power rating is linearly derated from tab = 25degC to (zero power at ) Tjmax e.g. 150 or 175 degC

    As you are aware - the tab of a device is usually significantly hotter than 25 degC in operation ...


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    Re: Is FET operating withinin SOA?...Pulsed linear regulator

    Thanks woops sorry i realise the current scale doesnt show on the top post's waveform, here it is re-attached.



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