# Stable PWM during Voltage Loss

1. ## Stable PWM during Voltage Loss

Refer the attached schematics, I have a system as below, controller runs at 200 kHz. I have a requirement of interruption at the controller voltage for 50 μs, still during that I need to have the PWM running. I have one option to have hold circuit for the controller to stabilize the voltage, to avoid the big Cap to be used. I thought of using PLL in between. But the PLLs duplicates the frequency! What could be considered ? any suggestions.

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2. ## Re: Stable PWM during Voltage Loss

You want the PWM to stay running when the power is removed?

That will never happen, your best option is to move the PWM source to the plant end where the power is always present and then send it instructions from the controller.
Bear in mind that without the controller running, even if you could "loop the last PWM waveform" it wouldn't be possible to change the on/off ratio.

Brian.

3. ## Re: Stable PWM during Voltage Loss

You'll need to use the big cap.

But, if the interruption is only for 50µs, the cap shouldn't need to be that large.

4. ## Re: Stable PWM during Voltage Loss

Yes - a ckt that stores enough energy for operation for 50uS ride through ...

5. ## Re: Stable PWM during Voltage Loss

It would be useful to know what exactly your 'plant' is. And how often you require this 50uS hiatus?

If your plant is a motor, then maybe loss of pwm drive for 50uS can be tolerated simply through inertia.

6. ## Re: Stable PWM during Voltage Loss

The Plant is DC converter and the hiatus would be of 50ms in fact, during the startup. I was trying to figure out some alternative, aiming to avoid hold up cap.

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7. ## Re: Stable PWM during Voltage Loss

Hi,

Why do you say "big capacitor"? .. and what does it mean?
Physically big, or big capacitance value?

There is a relatively simple formula: delta_V = time × current / capacitance.

Klaus

8. ## Re: Stable PWM during Voltage Loss

Originally Posted by Seeker_IN
The Plant is DC converter and the hiatus would be of 50ms in fact, during the startup. I was trying to figure out some alternative, aiming to avoid hold up cap.
Your descriptions are incomplete and inconsistent. Very difficult to provide any meaningful suggestions.

9. ## Re: Stable PWM during Voltage Loss

Let me be very specific then, Let's say i have a FPGA(controller)having 50ms of bootup time. generating PWM of 200KHz regulating a Buck plant.Now, the idea is, without using any Hold up ckt for the FPGA Power supply, if the Power supply for the FPGA gets interrupted due to 'change' in Power Supply source, happening only once the board is powered up How could i maintain the PWM for the 50ms, as if i use PLL, it would be able to lock the frequency not the pulse width?

@KlausST : It's the Capacitor size which for 50ms duration and 5 Amps of Current points to 50mF Cap. My priority is to have small form factor for my application using small SMD components. So, I am trying to think on the alternate lines.

10. ## Re: Stable PWM during Voltage Loss

Clearly this is some specialised equipment which I do not understand (Buck plant?, 5amps?, unknown voltage?).

However the 'normal' way to bridge power outage would be by using a battery backup. LiPo is quite compact.

11. ## Re: Stable PWM during Voltage Loss

This sounds rather confused. Buffering the controller supply for 50 ms shouldn't be a problem, how 5 A and 50 mF come into play?

12. ## Re: Stable PWM during Voltage Loss

Hi,

I'm confused, too.
I also don't understand, why an FPGA comes into play...and boot time of it, and where the 5A are...

From post #1:
interruption at the controller voltage for 50 μs
...for this a 100uF capacitor should be well sufficient

Klaus

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13. ## Re: Stable PWM during Voltage Loss

having an intermediate stage which copies the gate drive PWM and keeps it going to the o/p when the input goes away - is a very unusual requirement - mainly because when you want to stop the plant it won't - it will keep going for at least 50mS - you will need to have a stop/reset signal for this intermediate stage, as well as the pwm input.

You could use a high speed pic ( or any uP with a PWM output section ) to look at the input pwm and re-create it on it o/p and hold it for 100mS say if the i/p goes low

You still need a local power supply for this intermediate section that can ride thru at least 100mS and then shut down ( or ramp down ) the pwm when the Vcc starts to fall,

a small PIC or other uP may only draw 10-20mA to do this ...

14. ## Re: Stable PWM during Voltage Loss

This is turning out to be a very weird thread where nobody really knows what's going on.

I strongly recommend we shut it down until OP can give a meaningful requirememt/ specification

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