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    Issues during attemp of implementation of "Matrix multiplication" Verilog project

    Hello,

    I am trying to implement Verilog (actually: mixed VHDL and Verilog) project for matrix multiplication from this WWW page:

    https://www.fpga4student.com/2016/12...n-Verilog.html

    The input and output data are stored in BRAMs from FPGA circuit. My target FPGA is Spartan6 (XC6SLX9) - here is link to FPGA board I am using:

    https://numato.com/docs/mimas-v2-spa...ith-ddr-sdram/

    I am using ISE 14.7 Webpack on Windows. My problem is that I don't know how to generate needed BRAMs using "Xilinx Core Generator". I earlier generated BRAMS using "Xilinx Core Generator" from "zero", but I don't know how to do that from existing code - given on project WWW page.

    There is also used Verilog library for fixed-point math operations. I just added code from this page to ISE .project:

    https://www.dropbox.com/sh/inydmxlfz...nav_tracking=1

    and this library is working properly. I also added code of used BRAMs to the ISE project entities:
    • Matrix_A
    • ROM
    • matrix_out


    During synthesis phase *.ngc files are created by software. Verilog module named "matrix_multiplication" is my top module. Synthesis phase of implementing top module is ended without errors, but during "translation phase" I have three errors related to BRAMs components.

    Here are translate errors:

    Code:
    ERROR:NgdBuild:604 - logical block 'matrix_A_u' with type 'Matrix_A' could not
       be resolved. A pin name misspelling can cause this, a missing edif or ngc
       file, case mismatch between the block name and the edif or ngc file name, or
       the misspelling of a type name. Symbol 'Matrix_A' is not supported in target
       'spartan6'.
    ERROR:NgdBuild:604 - logical block 'matrix_B_u' with type 'ROM' could not be
       resolved. A pin name misspelling can cause this, a missing edif or ngc file,
       case mismatch between the block name and the edif or ngc file name, or the
       misspelling of a type name. Symbol 'ROM' is not supported in target
       'spartan6'.
    ERROR:NgdBuild:604 - logical block 'matrix_out_u' with type 'matrix_out' could
       not be resolved. A pin name misspelling can cause this, a missing edif or ngc
       file, case mismatch between the block name and the edif or ngc file name, or
       the misspelling of a type name. Symbol 'matrix_out' is not supported in
       target 'spartan6'.
    ANd here is output from ISE console (only translate phase):

    Code:
    Process "Synthesize - XST" completed successfully
    
    Started : "Translate".
    Running ngdbuild...
    Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-tqg144-3 matrix_multiplication.ngc matrix_multiplication.ngd
    
    Command Line: E:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
    ise -dd _ngo -nt timestamp -i -p xc6slx9-tqg144-3 matrix_multiplication.ngc
    matrix_multiplication.ngd
    
    Reading NGO file
    "C:/Users/MGabryelski.FAM/Spartan6/Matrix4DimMultiplyVerilog/matrix_multiplicati
    on.ngc" ...
    Loading design module
    "C:\Users\MGabryelski.FAM\Spartan6\Matrix4DimMultiplyVerilog/Matrix_A.ngc"...
    Loading design module
    "C:\Users\MGabryelski.FAM\Spartan6\Matrix4DimMultiplyVerilog/ROM.ngc"...
    Gathering constraint information from source properties...
    Done.
    
    Resolving constraint associations...
    Checking Constraint Associations...
    Done...
    
    Checking expanded design ...
    ERROR:NgdBuild:604 - logical block 'matrix_A_u' with type 'Matrix_A' could not
       be resolved. A pin name misspelling can cause this, a missing edif or ngc
       file, case mismatch between the block name and the edif or ngc file name, or
       the misspelling of a type name. Symbol 'Matrix_A' is not supported in target
       'spartan6'.
    ERROR:NgdBuild:604 - logical block 'matrix_B_u' with type 'ROM' could not be
       resolved. A pin name misspelling can cause this, a missing edif or ngc file,
       case mismatch between the block name and the edif or ngc file name, or the
       misspelling of a type name. Symbol 'ROM' is not supported in target
       'spartan6'.
    ERROR:NgdBuild:604 - logical block 'matrix_out_u' with type 'matrix_out' could
       not be resolved. A pin name misspelling can cause this, a missing edif or ngc
       file, case mismatch between the block name and the edif or ngc file name, or
       the misspelling of a type name. Symbol 'matrix_out' is not supported in
       target 'spartan6'.
    
    Partition Implementation Status
    -------------------------------
    
      No Partitions were found in this design.
    
    -------------------------------
    
    NGDBUILD Design Results Summary:
      Number of errors:     3
      Number of warnings:   0
    
    Total REAL time to NGDBUILD completion:  1 sec
    Total CPU time to NGDBUILD completion:   1 sec
    
    One or more errors were found during NGDBUILD.  No NGD file will be written.
    
    Writing NGDBUILD log file "matrix_multiplication.bld"...
    
    Process "Translate" failed
    Could somebody help me with these issues?

    Here is zipped ISE 14.7 project, and is second file zipped console output (all phases).


    Thanks in advance and regards.
    Last edited by FlyingDutch; 10th July 2019 at 12:07.

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    Re: Issues during attemp of implementation of "Matrix multiplication" Verilog project

    Hello,

    probalby I know what is up I just realize that I have to generate BRAM using "Core generator": XilinxCoreLib.blk_mem_gen_v6_1 .

    I someone could confirm/deny I would appreciate this.

    Regards



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    Re: Issues during attemp of implementation of "Matrix multiplification" Verolig proje

    You need to include the xci or ngc file in your project for the BRAMs.

    You would typically use ngc when you manage the IP separately from your project. If you included the xci then you also need to select the xci in the project and tell the tools to regenerate the IP.


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    Re: Issues during attemp of implementation of "Matrix multiplification" Verolig proje

    I someone could confirm/deny I would appreciate this.
    Yes, use Core Generator to generate.

    Otherwise consult the Xilinx ISE Synthesis guide in which there probably are RTL templates which infer BRAM.
    FPGA enthusiast!


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