Anomis
Junior Member level 3
- Joined
- Mar 11, 2017
- Messages
- 29
- Helped
- 5
- Reputation
- 10
- Reaction score
- 4
- Trophy points
- 3
- Location
- South Korea
- Activity points
- 294
Hi everybody,
I am playing with 65nm samsung process and do explore some parasitics components in the straightforward testbench below:
But the extracted cgsl(overlap capacitance between gate and lightly-doped source region) seems to be highly huge here : 96pF, that shall short G and S @high frequency design ( the model employed in this process here i guess could be the BSIM4). It is so weird.
could anybody have expertise in this stuff? please help me
thank you!!
I am playing with 65nm samsung process and do explore some parasitics components in the straightforward testbench below:
But the extracted cgsl(overlap capacitance between gate and lightly-doped source region) seems to be highly huge here : 96pF, that shall short G and S @high frequency design ( the model employed in this process here i guess could be the BSIM4). It is so weird.
could anybody have expertise in this stuff? please help me
thank you!!