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  1. #1
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    Problem with UART clock value in a VHDL sample code

    Hi, I'm using a VHDL code downloaded from GitHub to Drive a UART communication.
    Here
    I want to Use 250000 Baud Rate. So according to the top of VHDL file explanation, while my I_clk is 50MHz, I set:
    I_clk_baud_count <= X"00C8";--means 200

    it seems that the tx_clk should be 40us, but it is 40040ns in simulation.
    Is it wrong according to the code?
    Click image for larger version. 

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  2. #2
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    Re: Problem with UART clock value in a VHDL sample code

    Hi,

    40040ns is about 40us. There is just 0.1% difference. Thus it's well within UART frequency tolerance.

    On the other side...with a 50MHz input clock you should be able to generate exactly 40000ns.

    Klaus
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  3. #3
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    Re: Problem with UART clock value in a VHDL sample code

    Problem is that the generated timings are off by one count. The code is reproducing a popular VHDL beginners fault.

    Instead of
    Code VHDL - [expand]
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    if tx_clk_counter = 0 then
        -- chop off LSB to get a clock
        tx_clk_counter <= to_integer(unsigned(I_clk_baud_count(15 downto 1)));
        tx_clk <= not tx_clk;
    else
        tx_clk_counter <= tx_clk_counter - 1;
    end if;
    you want to write
    Code VHDL - [expand]
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    if tx_clk_counter = 0 then
        -- chop off LSB to get a clock
        tx_clk_counter <= to_integer(unsigned(I_clk_baud_count(15 downto 1)))-1;
        tx_clk <= not tx_clk;
    else
        tx_clk_counter <= tx_clk_counter - 1;
    end if;
    or
    Code VHDL - [expand]
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    if tx_clk_counter = 1 then
        -- chop off LSB to get a clock
        tx_clk_counter <= to_integer(unsigned(I_clk_baud_count(15 downto 1)));
        tx_clk <= not tx_clk;
    else
        tx_clk_counter <= tx_clk_counter - 1;
    end if;
    Hope the other coding is of better quality. My preferred VHDL flavour uses unsigned type both for the baud parameter and the counters, instead of std_logic_vector and integer, involving many type conversions.

    - - - Updated - - -

    There are some problems involved with the code.

    red warning (likely to cause unexpected behavior) for using external input signal I_rx without synchronizing.

    yellow warning (causes difficulties with timing closure) for driving the transmitter with ripple clock I_rx instead of I_clk and a clock enable.



  4. #4
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    Re: Problem with UART clock value in a VHDL sample code

    Quote Originally Posted by matriX_1500 View Post
    ...
    I want to Use 250000 Baud Rate.
    ...
    it seems that the tx_clk should be 40us
    ...
    Hi,

    At 250kbps, the tx_clk should be 1b/(250kb/s) = 4us and not 40us.

    - - - Updated - - -

    I_clk_baud_count <= X"00C8";--means 200 . . . Nope

    I_clk_baud_count <= X"00C5";--means 200 . . . Yes
    -------------
    --Akanimo.



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  5. #5
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    Re: Problem with UART clock value in a VHDL sample code

    Post #1 picture actually shows 4.04 µs, 1% off. Period neither is nor should be 40 µs.

    - - - Updated - - -

    I_clk_baud_count <= X"00C8";--means 200 . . . Nope

    I_clk_baud_count <= X"00C5";--means 200 . . . Yes
    Please reconsider



  6. #6
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    Re: Problem with UART clock value in a VHDL sample code

    Yes,

    I_clk_baud_count <= X"00C5"; gives exactly 4us.
    -------------
    --Akanimo.



  7. #7
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    Re: Problem with UART clock value in a VHDL sample code

    Hi,

    At 250kbps, the tx_clk should be 1b/(250kb/s) = 4us and not 40us.
    True ... I didn't re calculate it.

    Klaus
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  8. #8
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    Re: Problem with UART clock value in a VHDL sample code

    I_clk_baud_count <= X"00C5"; gives exactly 4us.
    Don't see how. You can get an exact TX Baudrate of 250 Kbaud by setting the baud divider to 199 or 198 (X"00C7" or X"00C6" respectively). This way you are compensating the above discussed design error. The RX rate will be still incorrect, thus you better correct the design and use baud divider of 200 or X"00C8".



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  9. #9
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    Re: Problem with UART clock value in a VHDL sample code

    1bit/250kbps = 4us
    50e+6/250k = 200;

    200/16 = 12 Remainder 5
    12/16 = 0 Remainder 12

    Decimal(12) = Hex(C)
    Decimal(200) = Hex(C5)

    - - - Updated - - -

    Quote Originally Posted by FvM View Post
    Don't see how.
    For God's sake, I don't know how I got X"00C5" for 200 earlier on.

    I just recalculated and I got X"00C8". Sorry for the confusion.
    -------------
    --Akanimo.



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    Re: Problem with UART clock value in a VHDL sample code

    Quote Originally Posted by Akanimo View Post
    Decimal(200) = Hex(C5)
    the decimal value is even, the hex value is odd.



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