+ Post New Thread
Results 1 to 6 of 6
  1. #1
    Newbie level 3
    Points: 42, Level: 1

    Join Date
    May 2019
    Posts
    5
    Helped
    0 / 0
    Points
    42
    Level
    1

    Analog Design System(ADS) verilog_a_Tutorial_PSFETCV error

    Click image for larger version. 

Name:	error.png 
Views:	7 
Size:	62.4 KB 
ID:	153228
    I simulated the example of veriloga tutorial workshop
    but with error message that :
    Error detected by hpeesofsim during netlist flattening.
    `psfetv1' is an instance of an undefined model `psfetv'.
    How can i solve it?

    •   AltAdvertisement

        
       

  2. #2
    Advanced Member level 5
    Points: 16,320, Level: 30
    pancho_hideboo's Avatar
    Join Date
    Oct 2006
    Location
    Real Homeless
    Posts
    2,496
    Helped
    664 / 664
    Points
    16,320
    Level
    30

    Re: Analog Design System(ADS) verilog_a_Tutorial_PSFETCV error

    ADS is not an Analog Design System.
    It is an Advanced Design System.

    Show me netlist.

    Simply you don’t include model definition which is described by Verilog-A or ADSsim language.
    Last edited by pancho_hideboo; 22nd May 2019 at 14:39.



    •   AltAdvertisement

        
       

  3. #3
    Newbie level 3
    Points: 42, Level: 1

    Join Date
    May 2019
    Posts
    5
    Helped
    0 / 0
    Points
    42
    Level
    1

    Re: Analog Design System(ADS) verilog_a_Tutorial_PSFETCV error

    Click image for larger version. 

Name:	netlist.png 
Views:	7 
Size:	38.7 KB 
ID:	153236
    I am sorry to mistype the word.
    how could i inculde th e model
    this tutorial example workspace should not already fininshed?



    •   AltAdvertisement

        
       

  4. #4
    Advanced Member level 5
    Points: 16,320, Level: 30
    pancho_hideboo's Avatar
    Join Date
    Oct 2006
    Location
    Real Homeless
    Posts
    2,496
    Helped
    664 / 664
    Points
    16,320
    Level
    30

    Re: Analog Design System(ADS) verilog_a_Tutorial_PSFETCV error

    Quote Originally Posted by yyy963741tw View Post
    how could i inculde th e model
    Place model definition component in schematic.

    Quote Originally Posted by yyy963741tw View Post
    this tutorial example workspace should not already fininshed?
    I can not understand what you want to mean at all.
    Write sentences with correct grammer.



  5. #5
    Newbie level 3
    Points: 42, Level: 1

    Join Date
    May 2019
    Posts
    5
    Helped
    0 / 0
    Points
    42
    Level
    1

    Re: Analog Design System(ADS) verilog_a_Tutorial_PSFETCV error

    so i should copy the veriloga code into netlist?


    I mean this work provided by program tutorial . It Should be able to simulate normally . But it can't



    •   AltAdvertisement

        
       

  6. #6
    Advanced Member level 5
    Points: 13,653, Level: 28

    Join Date
    Apr 2014
    Posts
    2,135
    Helped
    857 / 857
    Points
    13,653
    Level
    28

    Re: Analog Design System(ADS) verilog_a_Tutorial_PSFETCV error

    Check the schematic in your tutorial. It seems that you missed to add some model/library include block which tells ADS about the model details.



--[[ ]]--