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  1. #1
    Member level 5
    Points: 732, Level: 5

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    Aug 2017
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    TSMC LVS errors after sealring

    I am using TSMC 65nm PDK for tape out. The LVS was clean before I add the sealring. However, when I added the sealring, the LVS complaint about 2 things:
    (A) Stamping conflict. Net VSS is selected for stamping.
    (B) the additional nets and instance. The additional device from the sealring is a lot of parallel conected caps, called C(CM).
    For (A), stamping conflict, I confirmed that it is due to the sealring has OD-CO combination and LVS consider it as a substrate pin. But the sealring is not connected to the core substrate VSS pin. The way I solved it was enclosing the sealring by pusb2 layer. Do you think this is the right way to do so? Or should I connect the seal ring to the core VSS?
    For (B), I checked the LVS rule file and isolated the device and discovered that a subcell in sealring lib is the reason of this C(CM) device. The LVS rule considers the combined layers in the subcell as CM caps. By checking the LVS rule file I have, I can think of 2 ways to solve this LVS error. The first way is: I commented the line in LVS rule file that define the C(CM). Then The LVS could not recognize the C(CM) hence it is clean again. The second way I can think of is that can I ask if there is a schematic or spice/LVS netlist file associate with the sealring layout? (for example, the ESD devices has no schematic but a spice model for LVS)

    Thank you very much

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  2. #2
    Advanced Member level 5
    Points: 8,111, Level: 21

    Join Date
    Apr 2016
    300 / 300

    Re: TSMC LVS errors after sealring

    Just waive these seal ring related issues, I can't see why they would matter.
    Really, I am not Sam.

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