Fully differential continuous time integrator

1. Fully differential continuous time integrator

Hello, I am designing an integrator of a continuous time sigma delta ADC using a fully differential amplifier on cadence with input freq 1.5MHz and sampling freq at the comparator 256MHz.
In the integrator we add resistance parallel to the cap to adjust the dc ,but it gives a dc gain (R2/R1) with a corner freq 1/(2(pi)R2*c) so what should be the range of the dc gain and the ratio between the corner freq and the i/p signal frequency to insure that it is operating in the integrating range after the corner frequency?

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2. Re: Fully differential continuous time integrator

In the integrator we add resistance parallel to the cap to adjust the dc
No, you don't if you want a true integrator. Adding parallel R creates a lossy integrator respectively first order low pass.

The "DC" of an integrator must be adjusted by negative feedback in the outer loop.

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3. Re: Fully differential continuous time integrator

Does this setup resemble yours? PWM is fed to a DCR integrator, so it is smoothed to a volt level in the range 0 to 5v. Duty cycle ranges from maximum to minimum. Output voltage is in a linear (or roughly linear) relationship to duty cycle.

RC values were adjusted so that the output waveform 'looks right'. The capacitor value is chosen so it discharges just slightly during idle gaps.

A parallel resistor is needed because without it the capacitor would maintain output voltage near 12V with hardly any drop. The parallel resistor value is chosen to create linear response of output V to duty cycle.

Originally 5v was the amplitude of pulses from the op amp. This resulted in 1.8v output voltage for 99% duty cycle. That was after much experimenting with RC values. Apparently some attenuation makes for better linear response.
Thus the incoming amplitude had to be raised so as to achieve an output range of 0 to 5v.

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