abimann
Member level 4
Hello Dears
Signal coming from raspberry and i check this by divide clk and send to leds. and also can output to monitor hdmi in use Mike Fiels projects.
But smth strange and i cannot deliver signal from raspberry to monitor make just pipe from FPGA Virtex4.
I found this link by other issue but very same , but cannot use fpga_editor : http://forums.xilinx.com/t5/7-Series-FPGAs/Route-Error-471-ISE-14-2/td-p/418307 how to check this ?
Signal coming from raspberry and i check this by divide clk and send to leds. and also can output to monitor hdmi in use Mike Fiels projects.
But smth strange and i cannot deliver signal from raspberry to monitor make just pipe from FPGA Virtex4.
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity hdmi_design is
Port ( led : inout std_logic_vector(3 downto 0) :=(others => '0');
debug : out std_logic;
btn : in std_logic;
hdmi_rx_n : in std_logic_vector(3 downto 0);
hdmi_rx_p : in std_logic_vector(3 downto 0);
hdmi_tx_p : out std_logic_vector(3 downto 0);
hdmi_tx_n : out std_logic_vector(3 downto 0));
end hdmi_design;
architecture Behavioral of hdmi_design is
signal hdmi_clk ,reset : std_logic;
signal tmds_in ,tmds_out : std_logic_vector(3 downto 0);
begin
process (hdmi_clk,reset) -- blinker
variable count: integer range 0 to 48000000 := 0;
begin
if (reset = '0') then
count := 0; led <= "0000";
elsif (hdmi_clk'event and hdmi_clk = '1') then --
count := count + 1;
if (count = 48000000) then
led(0) <= not led(0); count := 0;
elsif (count = 36000000) then
led(1) <= not led(1);
elsif (count = 24000000) then
led(2) <= not led(2);
elsif (count = 12000000) then
led(3) <= not led(3);
end if;
end if;
end process;
debug <= tmds_in(3);
tmds_out <= tmds_in;
hdmi_clk <= tmds_in(3);
in_clk_buf: IBUFDS generic map ( IOSTANDARD => "LVDSEXT_25")
port map ( I => hdmi_rx_p(3), IB => hdmi_rx_n(3), O => tmds_in(3));
in_rx0_buf: IBUFDS generic map ( IOSTANDARD => "LVDSEXT_25")
port map ( I => hdmi_rx_p(0), IB => hdmi_rx_n(0), O => tmds_in(0));
in_rx1_buf: IBUFDS generic map ( IOSTANDARD => "LVDSEXT_25")
port map ( I => hdmi_rx_p(1), IB => hdmi_rx_n(1), O => tmds_in(1));
in_rx2_buf: IBUFDS generic map ( IOSTANDARD => "LVDSEXT_25")
port map ( I => hdmi_rx_p(2), IB => hdmi_rx_n(2), O => tmds_in(2));
out_clk_buf: OBUFDS generic map ( IOSTANDARD => "LVDSEXT_25", SLEW => "FAST")
port map ( O => hdmi_tx_p(3), OB => hdmi_tx_n(3), I => tmds_out(3));
out_tx0_buf: OBUFDS generic map ( IOSTANDARD => "LVDSEXT_25", SLEW => "FAST")
port map ( O => hdmi_tx_p(0), OB => hdmi_tx_n(0), I => tmds_out(0));
out_tx1_buf: OBUFDS generic map ( IOSTANDARD => "LVDSEXT_25", SLEW => "FAST")
port map ( O => hdmi_tx_p(1), OB => hdmi_tx_n(1), I => tmds_out(1));
out_tx2_buf: OBUFDS generic map ( IOSTANDARD => "LVDSEXT_25", SLEW => "FAST")
port map ( O => hdmi_tx_p(2), OB => hdmi_tx_n(2), I => tmds_out(2));
IBUF_inst_puW : IBUF -- pushW
port map ( O => reset, I => btn );
end Behavioral;
Code:
NET hdmi_rx_p<3> LOC = C33 | IOSTANDARD= LVDSEXT_25 | CLOCK_DEDICATED_ROUTE = FALSE; #pos J4.74_C33 (IO_L7P_9)
NET hdmi_rx_n<3> LOC = C34 | IOSTANDARD= LVDSEXT_25 | CLOCK_DEDICATED_ROUTE = FALSE; #neg J4.71_C34 (IO_L7N_9)
NET hdmi_rx_p<2> LOC = F33 | IOSTANDARD= LVDSEXT_25 | CLOCK_DEDICATED_ROUTE = FALSE; #pos J4.77_F33 (IO_L14P_9)
NET hdmi_rx_n<2> LOC = F34 | IOSTANDARD= LVDSEXT_25 | CLOCK_DEDICATED_ROUTE = FALSE; #neg J4.80_F34 (IO_L14N_9)
NET hdmi_rx_p<1> LOC = H33 | IOSTANDARD= LVDSEXT_25 | CLOCK_DEDICATED_ROUTE = FALSE; #pos J4.79_H33 (IO_L22P_9)
NET hdmi_rx_n<1> LOC = H34 | IOSTANDARD= LVDSEXT_25 | CLOCK_DEDICATED_ROUTE = FALSE; #neg J4.82_H34 (IO_L22N_9)
NET hdmi_rx_p<0> LOC = J34 | IOSTANDARD= LVDSEXT_25 | CLOCK_DEDICATED_ROUTE = FALSE; #pos J4.83_J34 (IO_L29P_9)
NET hdmi_rx_n<0> LOC = K34 | IOSTANDARD= LVDSEXT_25 | CLOCK_DEDICATED_ROUTE = FALSE; #neg J4.86_K34 (IO_L29N_9)
NET "hdmi_tx_n<3>"LOC = "A21" | IOSTANDARD = LVDSEXT_25;# | #neg J4.49_A21 (IO_L21N_5)
NET "hdmi_tx_p<3>"LOC = "B21" | IOSTANDARD = LVDSEXT_25;# | #pos J4.52_B21 (IO_L21P_5)
NET "hdmi_tx_n<2>"LOC = "B26" | IOSTANDARD = LVDSEXT_25;# | #neg J4.55_B26 ----------------- CLOCK NEGATIVE
NET "hdmi_tx_p<2>"LOC = "A26" | IOSTANDARD = LVDSEXT_25;# | 58 ----------------- CLOCK POZITIVE
NET "hdmi_tx_n<1>"LOC = "B30" | IOSTANDARD = LVDSEXT_25;# | #neg J4.61_B30(IO_L18N_5
NET "hdmi_tx_p<1>"LOC = "A30" | IOSTANDARD = LVDSEXT_25;# | #pos J4.64_A30(IO_L18P
NET "hdmi_tx_p<0>"LOC = "B32" | IOSTANDARD = LVDSEXT_25;# | #pos J4.67_B32(IO_L31P_5)
NET "hdmi_tx_n<0>"LOC = "B33" | IOSTANDARD = LVDSEXT_25;# | #neg J4.70_B33(IO_L31N_5)
net btn loc = H30 | PULLUP;
net led<0> loc = K33 ;
net led<1> loc = L34 ;
net led<2> loc = L33 ;
net led<3> loc = M33 ;
#net J4_J5<164> loc = AF33 | IOSTANDARD = LVCMOS33 | PULLDOWN; # J5.84_AF33
#net J4_J5<165> loc = AE33 | IOSTANDARD = LVCMOS33 | PULLDOWN; # J5.85_AE33
#net J4_J5<166> loc = AC34 | IOSTANDARD = LVCMOS33 | PULLDOWN; # J5.86_AC34
net debug loc = AD34 | IOSTANDARD = LVCMOS33 | PULLDOWN; # J5.87_AD34
I found this link by other issue but very same , but cannot use fpga_editor : http://forums.xilinx.com/t5/7-Series-FPGAs/Route-Error-471-ISE-14-2/td-p/418307 how to check this ?