kiyoshi7
Newbie level 5
Hi, I'm trying to write a simple program for sending data from the fpga to a computer through a usb to rs232 converter, Ftdi Ft232rl. I want to send 2 bytes of data then '\r\n'. I am using a lattice MachXO3L-6900C FPGA and simulating with Active-HDL lattice edition. Also I am new to FPGAs so I dont really know what I am doing as I am teaching myself how to use it. Could someone help me find out what is going on and how to fix it. This is the overall view of the program
CompClock is always outputting the clock signals, in this case its 133Mhz from osc_int port (it is the clock generated by the fpga's internal osc) and the P_UARTCLOCK is a 10Mhz clock.
CompUart is supposed to output the serial data on P_UARTDAT, when it transfers 4 bytes UARTREADY pulses for one clock cycle and resets the module to send everything again. I'm having two problems that I have no Idea how to fix the uartclock and the uart compontent itself.
The Uartclock is working in the fpga but using a logic analyzer I found the it was outputting an unstable clock signal which switches between 1.33Mhz and 2Mhz waveform below. this clock signal is generated from the internal 133MHz by lattice's PLL, so I don't know why it is so far off. when simulating this works correctly and I have a 10MHz clock. this the the overall view of the clock component
the Uart component is outputting nothing on the fpga, though it outputs on the simulation. So I have no Idea what might be wrong other than the clock here is the map for the uart component
I am keeping every file on github **broken link removed** in case if someone wants to see.
The the structure in the VHDL files is like this
Main
here is the vhdl main vhdl File and the clock vhdl file
CompClock is always outputting the clock signals, in this case its 133Mhz from osc_int port (it is the clock generated by the fpga's internal osc) and the P_UARTCLOCK is a 10Mhz clock.
CompUart is supposed to output the serial data on P_UARTDAT, when it transfers 4 bytes UARTREADY pulses for one clock cycle and resets the module to send everything again. I'm having two problems that I have no Idea how to fix the uartclock and the uart compontent itself.
The Uartclock is working in the fpga but using a logic analyzer I found the it was outputting an unstable clock signal which switches between 1.33Mhz and 2Mhz waveform below. this clock signal is generated from the internal 133MHz by lattice's PLL, so I don't know why it is so far off. when simulating this works correctly and I have a 10MHz clock. this the the overall view of the clock component
the Uart component is outputting nothing on the fpga, though it outputs on the simulation. So I have no Idea what might be wrong other than the clock here is the map for the uart component
I am keeping every file on github **broken link removed** in case if someone wants to see.
The the structure in the VHDL files is like this
Main
- CompClock
CompPLL (Lattice generated)
- CompUART
CompRS232- CompDataSelect (where the 16 bits data is seperated into two and \r\n is sent one after the other)
here is the vhdl main vhdl File and the clock vhdl file
Code:
library ieee;
use ieee.std_logic_1164.all;
entity Main is
port (
--T_test: out std_logic;
P_UART_TX: out std_logic
);
end Main;
architecture behav of Main is
signal S_MainClock : STD_LOGIC :='0';
signal S_UARTClock : STD_LOGIC :='0';
signal S_TX_DATA : std_logic_vector(15 downto 0) := X"AB7C";
signal S_UART_READY: std_logic;
signal S_UART_RESET: std_logic :='1';
COMPONENT Clock
-- synthesis translate_on
port (stdby : in std_logic;
osc_int: out std_logic;
p_UartClock : out std_logic;
P_resetclock : out std_logic
);
END COMPONENT;
COMPONENT UART
PORT(
P_UARTDATA: out std_logic ;
UARTREADY: out std_logic;
P_CLK: in std_logic;
P_Data: in std_logic_vector(15 downto 0);
P_Reset: in std_logic;
P_STDBY: in std_logic
);
END COMPONENT;
begin
CompClock: Clock
-- synthesis translate_on
PORT MAP(
STDBY => '0',
osc_int => S_MainClock,
p_UartClock => S_UARTClock,
P_resetclock => S_UART_RESET
);
CompUART: UART
PORT MAP(
P_UARTDATA => P_UART_TX,
UARTREADY => S_UART_READY,
P_CLK => S_UARTClock,
P_Data => S_TX_DATA,
P_Reset => S_UART_READY,--S_UART_RESET,
P_STDBY => '0'
);
--T_TEST <= S_UARTClock;
end behav;
Code:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- For Main Clock --
library machXO3l;
use machXO3l.all;
--------------------
entity Clock is
port (stdby : in std_logic;
osc_int: out std_logic;
p_UartClock : out std_logic;
P_resetclock : out std_logic
);
end Clock;
architecture Clock_behav of Clock is
signal S_InternalClock : std_logic;
signal S_mainClock : std_logic;
signal S_UARTClock : std_logic;
signal S_PLLEN : std_logic;
signal CLK_DIV : std_logic_vector (13 downto 0) := (others => '0');
COMPONENT OSCH
-- synthesis translate_off
GENERIC (NOM_FREQ: string := "133.00");
-- synthesis translate_on
PORT (STDBY : IN std_logic;
OSC : OUT std_logic
);
END COMPONENT;
attribute NOM_FREQ : string;
attribute NOM_FREQ of Clock : label is "133.00";
COMPONENT ClkPll
-- synthesis translate_on
PORT (CLKI : IN std_logic;
ENCLKOP : IN std_logic;
CLKOP : OUT std_logic;
ENCLKOS : IN std_logic;
CLKOS : OUT std_logic
);
END COMPONENT;
begin
Clock: OSCH
-- synthesis translate_off
GENERIC MAP( NOM_FREQ =>"133.00" )
-- synthesis translate_on
PORT MAP ( STDBY => '0',
OSC => S_InternalClock
);
CompPll: ClkPll
Port Map( CLKI => S_InternalClock,
ENCLKOP => S_PLLEN,
CLKOP => S_UARTClock,
CLKOS => S_mainClock,
ENCLKOS => '1'
);
-- clock divider
process (S_UARTClock)
begin
if (rising_edge(S_UARTClock)) then
CLK_DIV <= CLK_DIV + '1';
end if;
end process;
S_PLLEN <= not stdby;
osc_int <= S_mainClock;
p_UartClock <= S_UARTClock;
P_resetclock <= CLK_DIV(13);
end Clock_behav;