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Extra layers in finfet technologies

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nishant_16

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why we are using extra layers in finfet layouts like,diffcon,polycon,etc. as compared to that of cmos layouts
 

Foundries can name their layer names as needed. diffcon probably is a connection for a diffusion (which, itself, is an implant), so probably polycon is a connection layer to poly.
 

In FinFET technologies, the structure of device (transistors) is much more complex than for planar devices.

So, in additional to BEOL (Back End Of Line) layers, foundry are using MEOL (Middle End Of Line) layers (M0, local interconnects, etc.) to properly describe the system, its resistive and capacitive properties.

The BEOL description is practically the same for FinFETs and planar technologies (of course, dimensional scaling leads to new nonlinear effects in the BEOL, more complexity, etc.).
 

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