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    Design of a linear low-dropout voltage regulator in 0.18um cmos technology

    This is my schematic circuit using cadence software. Can anyone teach how to simulate the circuit in transient and ac simulation. Thanks.
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    Table below shows the dimension and parameter for the ldo.
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    Figure below shows the dc simulation result but I not sure whether is correct or not.
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    Please help me and if there is any resources kindly share me thanks.

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    Re: Design of a linear low-dropout voltage regulator in 0.18um cmos technology

    Why are your input diff pair transistors so different in size?



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    Re: Design of a linear low-dropout voltage regulator in 0.18um cmos technology

    Your pass FET is tiny and you have not said what the
    range of load current might be. Nor what the range of
    supply and output voltage setpoint may be. It appears
    the stack height is over-large, as you don't enter
    regulation until 1.5V and you are using all 1.8V
    transistors. Despite everything being cascoded you
    seem to show a not-great PSRR (w/ curvature) in the
    first sim plot. Your feedback ladder appears to be
    taking a few hundred uA, which might be too much
    for the small pass FET (?) at modest overdrive and
    linear-region. You "test" it by imposing much less
    external load current - kooky.


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    Re: Design of a linear low-dropout voltage regulator in 0.18um cmos technology

    Quote Originally Posted by sutapanaki View Post
    Why are your input diff pair transistors so different in size?
    Because I need to make all transistor to operate in saturation region. But at last i still cant make it by changing its width and length. So, what i can do to solve this problem. Thanks.



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    Re: Design of a linear low-dropout voltage regulator in 0.18um cmos technology

    Quote Originally Posted by sutapanaki View Post
    Why are your input diff pair transistors so different in size?
    Here is the table for the region for each of transistor
    Click image for larger version. 

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    Re: Design of a linear low-dropout voltage regulator in 0.18um cmos technology

    Thanks for the reply.
    Here is my parameter for the design.
    Input voltage = 1.65 V to 2 V
    Output voltage = 1.6 V
    Load current range = 9uA to 1.1mA
    Is it possible to make that?



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    Re: Design of a linear low-dropout voltage regulator in 0.18um cmos technology

    Quote Originally Posted by chenkhai95 View Post
    Because I need to make all transistor to operate in saturation region. But at last i still cant make it by changing its width and length. So, what i can do to solve this problem. Thanks.
    Get rid of some stack height, which eats headroom.

    Not all transistors get to be in saturation, all the time.
    Regardless what you may think you want or "need".
    Sometimes you just have to deal with that.

    - - - Updated - - -

    Quote Originally Posted by chenkhai95 View Post
    Thanks for the reply.
    Here is my parameter for the design.
    Input voltage = 1.65 V to 2 V
    Output voltage = 1.6 V
    Load current range = 9uA to 1.1mA
    Is it possible to make that?
    Possible? Probably.

    You need to first get to a pass FET which will throw
    2mA @ VTP-1V (or so) and 50mV Vds at slow*cold
    (worst case VT) and slow*hot (worst case IDsat@Vgs)
    and leak less than 1uA @ fast*hot, Vds=0.5V (make that
    Vds=2V, if this LDO is supposed to also remove power
    (e.g. for standby current spec).

    Your pass FET should for sure come from the ESD library
    (if FETs are there) or have ESD rules checked in the
    symbol & PCell (when you get to layout). That's a pin-pin
    pinata device application.



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    Re: Design of a linear low-dropout voltage regulator in 0.18um cmos technology

    May i know how to perform the transient analysis and ac analysis for the circuit. How to setup and need to place what component in the schematic in order to perform the analysis. For example, I need to find out line regulation, load regulation, transient response, open-loop gain and phase.



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