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  1. #1
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    BGA Power Decaps Routing_ BGA TOP_DECAPS BOTTOM LAYER

    I am using a BGA and unable to understand how to route the decaps of power line

    Ideally as shown in image below FPGA_3V3 should go to decap first and then to active part (FPGA Power)

    Due to space constraints and fan out taken, I have a via between active part and decap and that via connects to FPGA_3V3 and thereby the entire idea of having a decap seems to go for a toss.

    Image 3 shows how the decap is connected.


    Can anyone suggest me the best way to route the decaps.


    Since there are a lot of them (on FPGA_3V3, FPGA_2V5 and FPGA_1V1), i had planned to keep FPGA on Top layer and Decaps (0402) and bottom. I hardly have a option to use both on same layer.

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    Re: BGA Power Decaps Routing_ BGA TOP_DECAPS BOTTOM LAYER

    The via connecting to the BGA pad should be in the cap pad. It looks like you've got it right. Why do you think this "goes for a toss"? The whole point is that you want the cap provide the little surges of current the BGA pin requires. By keeping trace length, and, therefore, inductance, at a minimum you keep those currents 'local' to the pin.



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    Re: BGA Power Decaps Routing_ BGA TOP_DECAPS BOTTOM LAYER

    The shown bypass cap routing is the best you can do with standard via technology. Shorter routes and higher wiring density can be achieved with VIPPO (via in pad plated over) technology, but it's more expensive and not necessarily required.



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  4. #4
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    Re: BGA Power Decaps Routing_ BGA TOP_DECAPS BOTTOM LAYER

    Quote Originally Posted by barry View Post
    The via connecting to the BGA pad should be in the cap pad. It looks like you've got it right. Why do you think this "goes for a toss"? The whole point is that you want the cap provide the little surges of current the BGA pin requires. By keeping trace length, and, therefore, inductance, at a minimum you keep those currents 'local' to the pin.

    Attached is the detail of how the routing is. Although the distance is less, the track first connects to the FPGA_3V3 plane and then to the decap which I somehow feel is a wrong way to do. Kindly check and let me know.



    I donot have space to take the pins out either



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    Re: BGA Power Decaps Routing_ BGA TOP_DECAPS BOTTOM LAYER

    It’s not the wrong way to do it. You need to think about the entire current path and what you are actually trying to accomplish with those caps. See post #2, and read up on decoupling.



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    Re: BGA Power Decaps Routing_ BGA TOP_DECAPS BOTTOM LAYER

    I didn't need post #4 to know how the routing looks like, it was obvious before. As said, it's the best you can do in the given situation.

    I'm often using similar routing scheme, example below

    Click image for larger version. 

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    Better alternative is only VIPPO style plugged via

    Click image for larger version. 

Name:	vippo.PNG 
Views:	3 
Size:	126.4 KB 
ID:	150982



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  7. #7
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    Re: BGA Power Decaps Routing_ BGA TOP_DECAPS BOTTOM LAYER

    Thank You. I will keep it as it is. Though I am used to routing it the other way as I was explaining. This time it just got too complex :)



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