Adnan86
Full Member level 2
Hi,
I want to design a system with VIVDAO 18.3 version(Virtex-7 and xc7vx485tffg1157-1) by using VHDL code and also used FP-IP (latency = 2) and RAM IP.
I saved numers in coe file: address 0 to end have these value= > c190 0000, 4118 0000,411c 0000,4000 0000, c000 0000, 4000 0000 , c000 0000 , ....
As I used floating point IP. fused multiply-add => Y = (AxB) + C; I want the program to read A,B,C in RAM and Save Y in RAM. my code works good but my answer happened with one loop delayed. instead, my answer saved in address = 03 , the answer (Y) saved in address = 6. I know maybe because of delay and latency, this is happend but how I can change code to fix this problem.
the code is:
and the wave:
I Will aprecite to help me.
I want to design a system with VIVDAO 18.3 version(Virtex-7 and xc7vx485tffg1157-1) by using VHDL code and also used FP-IP (latency = 2) and RAM IP.
I saved numers in coe file: address 0 to end have these value= > c190 0000, 4118 0000,411c 0000,4000 0000, c000 0000, 4000 0000 , c000 0000 , ....
As I used floating point IP. fused multiply-add => Y = (AxB) + C; I want the program to read A,B,C in RAM and Save Y in RAM. my code works good but my answer happened with one loop delayed. instead, my answer saved in address = 03 , the answer (Y) saved in address = 6. I know maybe because of delay and latency, this is happend but how I can change code to fix this problem.
the code is:
Code:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/29/2018 09:31:20 PM
-- Design Name: Adnan
-- Module Name: SP_RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SP_RAM is
Port (
----- Bit Control & Addess ------
clk : IN STD_LOGIC;
-- OP : IN STD_LOGIC;
rstN : IN STD_LOGIC;
-- addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
-- addrB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
-- addrC : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
-- addrOUT : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
-----------------------------------
------ Inputs data ----------------
-----------------------------------
------ Output datas --------------
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-- addr_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
Vout : OUT STD_LOGIC
----------------------------------
);
end SP_RAM;
architecture Behavioral of SP_RAM is
---------- RAM 32 bits ----------
COMPONENT dist_mem_gen_0
PORT (
a : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-----------------------------------
----------- Single Precision ---------
COMPONENT floating_point_0
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
--------------- Signals---------------
SIGNAL A: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL B: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL C: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL Y: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL d_in: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL d_out: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL address: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL addr : STD_LOGIC_VECTOR(4 DOWNTO 0):= "00000";
SIGNAL clkEN: STD_LOGIC;
SIGNAL VA: STD_LOGIC;
SIGNAL VB: STD_LOGIC;
SIGNAL VC: STD_LOGIC;
SIGNAL wrEN: STD_LOGIC;
SIGNAL count: integer := 0 ;
--------------------------------------
--------------- read & write and nothing state ----
-- s0 : nothing -- s1 : read -- s2 : write
TYPE state_type is (s0, s1, s2);
---- Siganl
SIGNAL state : state_type;
---------------------------------------------------
begin
--------------------------- Port Map RAM ----------------------------------
-------- Input & Output -------------
ram1 : dist_mem_gen_0
PORT MAP (
a => address,
d => d_in,
clk => clk,
we => wrEN,
spo => d_out
);
-----------------------------------
----------------------------------------------------------------------------
--------- Port Map SP -------------
sp1 : floating_point_0
PORT MAP (
aclk => clk,
aclken => clkEN,
aresetn => rstN,
s_axis_a_tvalid => VA,
s_axis_a_tdata => A,
s_axis_b_tvalid => VB,
s_axis_b_tdata => B,
s_axis_c_tvalid => VC,
s_axis_c_tdata => C,
m_axis_result_tvalid => Vout,
m_axis_result_tdata => Y
);
-----------------------------------
--data_out <= Y;
------------ Main Process ---------
PROCESS (clk, rstN)
--VARIABLE count: integer := 0 ;
BEGIN
IF rstN = '0' THEN
--A <= (OTHERS => '0');
--B <= (OTHERS => '0');
--C <= (OTHERS => '0');
--Y <= (OTHERS => '0');
--d_in <= (OTHERS => '0');
--d_out <= (OTHERS => '0');
address <= (OTHERS => '0');
addr <= (OTHERS => '0');
wrEN <= '0';
clkEN <= '0';
VA <= '0';
VB <= '0';
VC <= '0';
state <= s0; -- Do nothing
ELSIF clk'event AND clk = '1' THEN
CASE state IS
WHEN s0 =>
IF count /= 0 THEN
count <= 0;
clkEN <= '0';
address <= addr;
wrEN <= '0';
state <= s0;
VA <= '0';
VB <= '0';
VC <= '0';
ELSE
state <= s1;
clkEN <= '0';
address <= addr;
wrEN <= '0';
VA <= '0';
VB <= '0';
VC <= '0';
count <= 0;
END IF;
-- IF op = '0' THEN
-- count <= 0;
-- state <= s0;
-- clkEN <= '0';
-- wrEN <= '0';
-- VA <= '0';
-- VB <= '0';
-- VC <= '0';
-- address <= addr;
-- ELSE
-- state <= s1;
-- count <= 0;
-- wrEN <= '0';
-- clkEN <= '0';
-- address <= addr;
-- END IF;
WHEN s1 => -- read A
IF count = 0 THEN
A <= d_out;
VA <= '1';
count <= count +1;
address <= STD_LOGIC_VECTOR(UNSIGNED(addr) + 1);
-- address <= address + 1;
wrEN <= '0';
clkEN <= '0';
END IF;
IF count = 1 THEN -- Read B
B <= d_out;
VB <= '1';
count <= count +1;
address <= STD_LOGIC_VECTOR(UNSIGNED(addr) + 2);
wrEN <= '0';
clkEN <= '0';
END IF;
IF count = 2 THEN -- Read C
C <= d_out;
VC <= '1';
count <= count +1;
address <= STD_LOGIC_VECTOR(UNSIGNED(addr) + 3);
wrEN <= '0';
state <= s2;
clkEN <= '1';
END IF;
--IF count = 3 THEN -- Stay in Read Mode 1 clk more
--state <= s2;
--address <= STD_LOGIC_VECTOR(UNSIGNED(addr) + 3);
--END IF;
WHEN s2 => -- write
IF count = 3 THEN
d_in <= Y;
count <= count +1;
address <= STD_LOGIC_VECTOR(UNSIGNED(addr) + 3);
addr <= STD_LOGIC_VECTOR(UNSIGNED(address) );--+1
wrEN <= '1';
clkEN <= '1';
--state <= s0;
END IF;
IF count = 4 THEN
--IF d_in /= d_out THEN
--state <= s2;
--ELSE
--count <= count +8;
state <= s0;
--wrEN <= '0';
--clkEN <= '0';
--VA <= '0';
--VB <= '0';
--VC <= '0';
--data_out <= d_out;
--END IF;
END IF;
END CASE;
END IF;
END PROCESS;
---------------------------
---------------------------
--addr_out <= address;
data_out <= d_out;
----------------------------------
end Behavioral;
and the wave:
I Will aprecite to help me.