engr_joni_ee
Advanced Member level 3
Hello,
Is there any tool exist which convert Verilog to VHDL ?
Is there any tool exist which convert Verilog to VHDL ?
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I have found a working example in Verilog and I need to modify it but I need to do it in VHDL rather then Verilog.
Hello,
Is there any tool exist which convert Verilog to VHDL ?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 reg [C_AXIS_TDATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0]; reg [C_AXIS_TDATA_WIDTH+2-1:0] mem_read_data_reg = {C_AXIS_TDATA_WIDTH+2{1'b0}}; reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; wire [C_AXIS_TDATA_WIDTH+2-1:0] mem_write_data; reg [C_AXIS_TDATA_WIDTH+2-1:0] m00_data_reg = {C_AXIS_TDATA_WIDTH+2{1'b0}}; reg m00_axis_tvalid_reg = 1'b0, m00_axis_tvalid_next; // full when first TWO MSBs do NOT match, but rest matches // (gray code equivalent of first MSB different but rest same) wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && (wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && (wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0])); // empty when pointers match exactly wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg; // control signals reg write; reg read; reg store_output; assign s00_axis_tready = ~full & ~s00_rst_sync3_reg; assign m00_axis_tvalid = m00_axis_tvalid_reg; assign mem_write_data = {s00_axis_tlast, s00_axis_tdata}; assign {m00_axis_tlast, m00_axis_tdata} = m00_data_reg;
Code Verilog - [expand] 1 ]reg [C_AXIS_TDATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
Code Verilog - [expand] 1 reg [C_AXIS_TDATA_WIDTH+2-1:0] mem_read_data_reg = {C_AXIS_TDATA_WIDTH+2{1'b0}};
Code Verilog - [expand] 1 reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
Code Verilog - [expand] 1 2 3 4 5 // full when first TWO MSBs do NOT match, but rest matches // (gray code equivalent of first MSB different but rest same) wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && (wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && (wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
Code Verilog - [expand] 1 assign s00_axis_tready = ~full & ~s00_rst_sync3_reg;
Code Verilog - [expand] 1 assign m00_axis_tvalid = m00_axis_tvalid_reg;
Code Verilog - [expand] 1 assign mem_write_data = {s00_axis_tlast, s00_axis_tdata};
Code Verilog - [expand] 1 assign {m00_axis_tlast, m00_axis_tdata} = m00_data_reg;
I don't think there is an equivalent in VHDL
Is it possible to use 'signal' in VHDL in place of 'wire' and 'reg' in Verilog ?
reg [C_AXIS_TDATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
type ram_t is array(2**ADDR_WIDTH-1 downto 0) of std_logic_vector(C_AXIS_TDATA_WIDTH+2-1 downto 0);
signal mem : ram_t;
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 module axis_fifo_v1_0 # ( parameter ADDR_WIDTH = 12, parameter C_AXIS_TDATA_WIDTH = 32 ) ( input wire s00_axis_aclk, input wire s00_axis_aresetn, input wire [C_AXIS_TDATA_WIDTH-1:0] s00_axis_tdata, input wire [(C_AXIS_TDATA_WIDTH/8)-1 : 0] s00_axis_tstrb, input wire s00_axis_tvalid, output wire s00_axis_tready, input wire s00_axis_tlast, input wire m00_axis_aclk, input wire m00_axis_aresetn, output wire [C_AXIS_TDATA_WIDTH-1:0] m00_axis_tdata, output wire [(C_AXIS_TDATA_WIDTH/8)-1 : 0] m00_axis_tstrb, output wire m00_axis_tvalid, input wire m00_axis_tready, output wire m00_axis_tlast );
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 entity axis_fifo_v1_0_tb is end axis_fifo_v1_0_tb; architecture Behavioral of axis_fifo_v1_0_tb is component axis_fifo_v1_0 generic( ADDR_WIDTH : integer := 12; C_AXIS_TDATA_WIDTH : integer := 32 ); port ( s00_axis_aclk : in std_logic; s00_axis_aresetn : in std_logic; s00_axis_tdata : in std_logic_vector(C_AXIS_TDATA_WIDTH-1:0); s00_axis_tstrb : in std_logic_vector((C_AXIS_TDATA_WIDTH/8)-1 : 0); s00_axis_tvalid : in std_logic; s00_axis_tready : out std_logic; s00_axis_tlast : in std_logic; m00_axis_aclk : in std_logic; m00_axis_aresetn : in std_logic; m00_axis_tdata : out std_logic_vector(C_AXIS_TDATA_WIDTH-1:0); m00_axis_tstrb : out std_logic_vector(C_AXIS_TDATA_WIDTH/8)-1 : 0); m00_axis_tvalid : out std_logic; m00_axis_tready : in std_logic; m00_axis_tlast : out std_logic ); end component; begin end Behavioral;
assign s00_axis_tready = ~full & ~s00_rst_sync3_reg;
assign mem_write_data = {s00_axis_tlast, s00_axis_tdata };
assign {m00_axis_tlast, m00_axis_tdata} = m00_data_reg;
if ( (not(full)) and (not (s00_rst_sync3_reg))) then
s00_axis_tready <= '1';
else
s00_axis_tready <= '0';
end if;
# ** Error: E:/temp/ip_repo/hdl/AXIS_v1_0.vhd(154): Type error resolving infix expression "and" as type std.STANDARD.BOOLEAN.
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) &&
(wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) &&
(wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
// empty when pointers match exactly
wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg;
if ((wr_ptr_gray_reg(GC_ADDR_WIDTH) /= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH)) and
(wr_ptr_gray_reg(GC_ADDR_WIDTH-1) /= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH-1)) and
(wr_ptr_gray_reg(GC_ADDR_WIDTH-2 downto 0)= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH-2 downto 0))) then
full <= '1';
else
full <= '0';
end if;
if (rd_ptr_gray_reg = wr_ptr_gray_sync2_reg) then
empty <= '1';
else
empty <= '0';
end if;
assign s00_axis_tready = ~full & ~s00_rst_sync3_reg;
s00_axis_tready <= not (full) and not ((s00_rst_sync3_reg));
A quick way to check would be to run synthesis on each of the two codes and then compare the resulting circuits in RTL viewer.Hi,
Still something is not clear. I have converted a Verilog statement to VHDL.
Code:assign s00_axis_tready = ~full & ~s00_rst_sync3_reg;
Code:s00_axis_tready <= not (full) and not ((s00_rst_sync3_reg));
Is the above conversion is correct ?
- - - Updated - - -
wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg;
if (rd_ptr_gray_reg = wr_ptr_gray_sync2_reg) then
empty <= '1';
else
empty <= '0';
end if;
Code VHDL - [expand] 1 empty <= bool_to_std_logic(rd_ptr_gray_reg = wr_ptr_gray_sync2_reg);