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  1. #1
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    VHDL unconstrained array in VCS

    Hello,

    In my design I use arrays of unsigned vectors. For this purpose, I define an unconstrained array type inside a package as follows:
    Code:
    type generic_array_unsigned_1d is array ( natural range <> ) of unsigned ;
    In the source file where I use this type I define the signal as follows:
    Code:
    signal some_array_of_unsigned : generic_array_unsigned_1d is array ( 0 to some_depth - 1 ) ( some_width - 1 downto 0 ) ;
    The code compiles successfully with Modelsim / Questa , Vivado and Quartus.

    However, when I try to compile it with VCS - It fails on the line where the signal is declared with an obscure message:
    "Syntax error detected during VHDL parsing".
    * I verified that the tool is set to VHDL 2008.

    What might cause such an error ?

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  2. #2
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    Re: VHDL unconstrained array in VCS

    Id say the tool doesnt support unconstrained arrays. But I dont use VCS, and cannot find documentation about 2008 support.
    Have you raised a support ticket?



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  3. #3
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    Re: VHDL unconstrained array in VCS

    Yes. Waiting to hear back...



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