msdarvishi
Full Member level 4
Hi,
I am working wothCicado 3017.3 targeting a zc706 board.
I am trying to write some data in the DDR3 of PL and then use AXI DMA (or CDMA, I am a liitlebit confused which one) to read that data from DDR3-PL and write into a Block RAM. My design proposal is like below. I have implemented and generated bitstream.
In this design, I write a datato DDR3-PL through PCIe and they try to transfer it to the BRAM via Zynq Processor in SDK.
I could write data to DDR3-PL via PCIe, but when I read the content of BRAM, it is not identical with datain DDR3-PL.
Can anyone help me to solve this issue? Thanks in advance for your support.
Best,
Daryon
I am working wothCicado 3017.3 targeting a zc706 board.
I am trying to write some data in the DDR3 of PL and then use AXI DMA (or CDMA, I am a liitlebit confused which one) to read that data from DDR3-PL and write into a Block RAM. My design proposal is like below. I have implemented and generated bitstream.
In this design, I write a datato DDR3-PL through PCIe and they try to transfer it to the BRAM via Zynq Processor in SDK.
I could write data to DDR3-PL via PCIe, but when I read the content of BRAM, it is not identical with datain DDR3-PL.
Can anyone help me to solve this issue? Thanks in advance for your support.
Best,
Daryon