filip.amator
Full Member level 3
I am trying to fix my design, it works in the ModelSim but doesn't work in the hardware. I ran gate level simulation (with the same test bench) but shortly after starting some debug at the output of the FPGA signals got 'X'. Is there any way to track where and when 'X' appears inside the design? All input data from memory are defined. I have an access to some Mentor's tools (QuestaSim, Precision Synthesis etc).