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[SOLVED] FPGA coding style behavioral vs structural modeling

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Re: FPGA coding style Behavioural vs structural Modelling

eengr said:
am struggling to find any delays in my DUT code as I haven't used any counter/timers for any delays in my code. I am using same DUT code as in my post #15
Click to expand...

Code VHDL - [expand]
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if (rising_edge (ISA_CLK)) then
 
                        if (ISA_IOW = '0' and ISA_IOR = '1') then -- Write is enabled

All the outputs generated from the DUT are delayed by 1 clock cycle resulting in the X's you see, as the outputs aren't updated until the rising edge of the clock while the IOW/IOR are in the correct state.
 
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Re: FPGA coding style Behavioural vs structural Modelling

ads-ee said:
All the outputs generated from the DUT are delayed by 1 clock cycle resulting in the X's you see, as the outputs aren't updated until the rising edge of the clock while the IOW/IOR are in the correct state.
Click to expand...

Hmm that means in actual hardware I could have bus contention!?

Or may be NOT as Master should be in Data Read mode before it sends the signal out IOR to Low & IOW to HIGH

But then I would need to check ISA_CLK signal from Master in my code to use it as Clocking signal for the IO registers

I am not sure if I have a problem here or not... Any suggestions!
 

Re: FPGA coding style Behavioural vs structural Modelling

Ok I have now manged to test the code on hardware and it is behaving (functional testing so far).

However, when I generated the .bit file, Xilinx ISE gave the following error:

Code VHDL - [expand]
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ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component <ISA_CLK> is placed at site <P1>. The corresponding BUFG
   component <ISA_CLK_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y3>. There is
   only a select set of IOBs that can use the fast path to the Clocker buffer,
   and they are not being used. You may want to analyze why this problem exists
   and correct it. If this sub optimal condition is acceptable for this design,
   you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote
   this message to a WARNING and allow your design to continue. However, the use
   of this override is highly discouraged as it may lead to very poor timing
   results. It is recommended that this error condition be corrected in the
   design. A list of all the COMP.PINs used in this clock placement rule is
   listed below. These examples can be used directly in the .ucf file to
   override this clock rule.
   < NET "ISA_CLK" CLOCK_DEDICATED_ROUTE = FALSE; >


I was not sure about the cause of this error so I just added the last line:

Code VHDL - [expand]
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NET "ISA_CLK" CLOCK_DEDICATED_ROUTE = FALSE;


in my constraints file & the error disappeared.

My 1st question: is it the correct way of dealing with the above error? Could I get any problems later on due to this issue?

Second question I have used 4 Addresses in my code as:

Code VHDL - [expand]
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if (ISA_ABUS_IN = X"0500")
 
-----------
-----------
elsif (ISA_ABUS_IN = X"0501")
 
--- ETC


& then another for 0x0502

Is there a way to declare these addresses as variables with some name like: Address1, Address2, etc on the top near Signals and initialise them with the address values e.g.,
Address1 = 0x0500
Address2 = 0x0501
Address3 = 0x0502

and so on

& then I use "Address1" in the if statement instead of its actual value?

What is the syntax to do like this in VHDL?
 

Re: FPGA coding style Behavioural vs structural Modelling

Code VHDL - [expand]
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constant ADDRESS1 : std_logic_vector(15 downto 0) := X"0500";


The error you had means you used or added placement constraints that caused the tools to place the clock input on a pin that does not have a direct route to the clock buffer. The added line in the constraints lets the tools route the clock on fabric resources to get to the clock buffer, which can vary from build to build.

Unless you post the part, package, pinout, constraints and any code that has to do with the clock can't help further.
 
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Re: FPGA coding style Behavioural vs structural Modelling

ads-ee said: 
Code VHDL - [expand]
1

constant ADDRESS1 : std_logic_vector(15 downto 0) := X"0500";


The error you had means you used or added placement constraints that caused the tools to place the clock input on a pin that does not have a direct route to the clock buffer. The added line in the constraints lets the tools route the clock on fabric resources to get to the clock buffer, which can vary from build to build.

Unless you post the part, package, pinout, constraints and any code that has to do with the clock can't help further.
Click to expand...

Thank you very much for your & FvM's help.

Regarding CLK, I changed it to another pin that has GCCLK in its description & the error disappeared which means I had to cut couple of tracks and use a jumper wire for these prototype boards but they are working now. :)
 

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