To improve test-ability during scan we are thinking of splitting the functional reset in to 2 resets, being dft reset and system reset, during scan test mode.
Which means, while in scan test mode the tap controller can not be reset and the system reset will follow the reset input pin without being synchronized.
The ATPG tools can most probably get better coverage when it has control of the reset.

To gain control over the functional reset again:
- a power down is required
- the Tap controller needs to be put in test logic reset

I see a possible dead-lock/unwanted situation.

What is best practice in this case ?
We are pad limited so do not have the luxury to add a trts_n. Currently the trst_n is connected to system reset.