Clock source switching

I am designing Main board using Altera FPGA. In circuit I need external differential clock. On main board I have introduce one clock generator circuit also have provision to take clock from external daughter board. Clock frequency range is 10-200 MHz. There are two possibilities but at time one source is selected
1) On board clock generation to FPGA
2) From external board to FPGA
In this can I use male berg pin for clock source selection between on board circuit or external board? If I use Berg pin does it affect on clock signal in any way?
I can use clock multiplexing IC, still it will increase lot of hardware as I have 4 clock input signals. One more option to place clock generation circuit near possible to header and directly shorting trace without any jumper?
Does Berg pin harm in this condition? If yes what are the different effect on clock signal?
If I directly merge the both signals what are the different effect of same.
As I have seen lot of board on which berg pin jumper is used for selection clock source but it have smaller frequency range like 5 MHz. One of the reference from Microchip is here. https://www.microchip.com/webdoc/stk500/stk500.clock.settings.html

Only vague description of involved IO-standard. Differential clock suggests an impedance matched IO-standard like LVDS. And a double throw 0.1" jumper (6 pins, 2 jumpers). What is it? Please give a complete description.

I would prefer smaller jumpers, e.g. 2 mm which introduce less transmission line discontinuity. You should also consider the behavior of the unconnected and unterminated clock source, it may cause a lot of noise.

Using two clock input pairs on the FPGA and internal clock source switching can be an alternative.

Hi,

You must not connect two (clock) sources to one signal node without control.
If it's impossible to switch one clock source output to HIGH-Z, then use a MUX.(intern - with two seperated inputs - or extern of FPGA)

Klaus

FPGA I/O is working on 2.5V and I/O standard can LVTTL or LVCMOS. yes your right two jumper must be use as it is differential. But don't know what will be the effect of jumpers on clock signal. As only one clock source is present at time(clock signal will not present on traces but still traces can act as stub to other clock source signal if I connect them directly) so I want to isolate other clock source traces from circuit to less effect on clock signal.
if I use jumper so clock selection them it will act as single clock trace line with berg pin jumper but other clock trace also get removed. in such case what will be the effect of berg pin jumper on clock signals.

yes your right!

At a time one clock source signal are present on lines but layout traces from other source will be act as stub to clock signal if i don't physically isolate trace form second source. for that purpose i am finding to trace isolation without affecting clock signal

Hi,

You may place the jumpers as close as possible to the FPGA and put two individual termiation resistors on eaxh pair in front of the jumpers.
The short traces from jumper to FPGA won´t be problematic.

An alternaitve is are CMOS switches, a CMOS MUX, clock buffers with output_enable...

Also you may consider to use differential-to-singleended converters and run the last few millimeters to the FPGA single ended. And use single throw jumpers, MUX....

Klaus