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VHDL substitute text to simplify code.

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buenos

buenos

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Hi,
Is there a way in VHDL to automatically substitute some pre-defined text to simplify code?
I have hundreds of these:
device_status(7+8*24 downto 0+8*24) <= "01000001";

But I would like to define a string like this:
msb = "7+8*"
lsb = "0+8*"
Then write the code like this:
device_status(msb*24 lsb*24) <= "01000001";
or even like this:
device_status(xyz(24)) <= "01000001";

or maybe define a whole list of:
"index_0" = (7+8*0 downto 0+8*0)
"index_1" = (7+8*1 downto 0+8*1)
...
then use it as:
device_status(index_24) <= "01000001";


Is there a way to do such simplification?
 

A lesser known VHDL trick is that subtypes can be used as a range.
Code: 
subtype kMyRange is integer range 31 downto 0;  
signal myThirtyTwoBitVector : std_logic_vector(kMyRange);

The subtype can be used where a range would be used -- including loops and indexing.

You may also be able to use a function. I get the feeling that this won't work though:
Code: 
function myFunction(constant integer x) return std_logic_vector is
  constant ret : std_logic_vector(32*(x+1)-1 downto 32*x) := (others => '0');
begin
  return ret;
end function;

signal mySignal(63 downto 0);

mySignal(myFunction(0)'range) <= mySignal(myFunction(1)'range);
 

VHDL has no Precompiler like C or Verilog. So, the short answer is NO.

@vGoodTimes
The function should work fine.

@OP ou may want to look at re-coding what you have to something simpler. Have you considered other things, like using aliases or functions to get what you want?

Code VHDL - [expand]
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op : out std_logic_vector(31 downto 0);
 
....
 
alias op_byte0 : std_logic_vector(7 downto 0) is op( 7 downto  0);
alias op_byte1 : std_logic_vector(7 downto 0) is op(15 downto  8);
alias op_byte2 : std_logic_vector(7 downto 0) is op(23 downto 16);
alias op_byte3 : std_logic_vector(7 downto 0) is op(31 downto 24);
 
....
 
op_byte0 <= x"00";
op_byte1 <= x"11";
op_byte2 <= x"22";
op_byte3 <= x"33";


How big is this device status bus? would it be easier just to have lots of separate signals you just combine later? Usually this is easier to debug.
if you post the whole code, it might be easier to give you a more specific example.
 

Hi,
Thanks.
Finally I decided to combine by long vectors to 2D arrays, and index the arrays instead.
That required a "GENERATE", be used, otherwise it would have been thousands of lines of code.
That simplifies the assignments to:
device_status_array(24) <= "01000001";
 

With this, it might also be useful to have conversion functions to convert between types.

Code VHDL - [expand]
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type byte_array_t    is array( natural range <> ) of std_logic_vector(7 downto 0);
 
----------------------------------------------------------------------------------------------
-- Converts an array of slv to an array of bytes
----------------------------------------------------------------------------------------------
function to_bytes( s          : std_logic_vector;
                   start_left : boolean       := true ) return byte_array_t is
  variable ret     : byte_array_t(0 to s'length/8 -1);
  alias    s_a_to  : std_logic_vector(0 to s'length-1    ) is s;
  alias    s_a_dt  : std_logic_vector(s'length-1 downto 0) is s;
begin
  assert s'length rem 8 = 0
    report "to_bytes : s must be a multiple of bytes"
      severity failure;
 
  if start_left then
    for i in ret'range loop
      ret(i)    := s_a_to( (i*8) to (i+1)*8 -1 );
    end loop;
 
  else
    for i in ret'range loop
      ret(i)    := s_a_dt( (i+1)*8 -1 downto (i*8) );
    end loop;
  end if;
 
  return ret;
end function to_bytes;
 
 
 
function to_slv(b : byte_array_t) return std_logic_vector is
  alias    b_a  : byte_array_t(0 to b'length-1) is b;
  variable ret  : std_logic_vector(0 to b'length*8-1);
begin
  for i in b_a'range loop
    ret( (i*8) to (i+1)*8-1 ) := b_a(i);
  end loop;
  
  return ret;
end function to_slv;
 

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