Characterizing cells with verilog-A models for components

frasheed said:

Hi, I am trying to characterize the basic cells (Inverter for example) using liberate 15. The technology we are using deosn't have a PMOS transistor so the inverter is implemented using T-R logic. The component models are written verilog-A format. I have extracted the netlist from Virtuoso ADE-L (simulation->netlist->create). I am developing standard cells for this technology and I am implementing this for the first time. My netlist and characterization script is given below:

Code:

;;;;Netlist (Input.scs)

simulator lang=spectre
global 0 VSS! VDD!

subckt INV_X1 A Y
    I1 (VDD! Y) res_route w=10u res=40K rL=5.405m
    I0 (Y A VSS!) negfet_route W=200u L=40u vth=0.1763 S=12.3591 \
        gamma=2.6983 K=1.38065e-23 T=300 q=1.60218e-19 f1=1.143e-05 \
        f2=1.605 f3=6.121 f4=0.0345 Rg=10
ends INV_X1
// End of subcircuit definition.

;;;Characterization Script (char.tcl)

# Define templates for characterization.
# Delay template for 3 input slews and 3 loads
define_template -type delay \
-index_1 {0.025 0.1 0.25} \
-index_2 {0.0010 0.015 0.100} \
delay_3x3
# Power template for 3 input slews and 3 loads
define_template -type power \
-index_1 {0.025 0.1 0.25} \
-index_2 {0.0010 0.015 0.100} \
power_3x3
# Timing constraint template for 3 input slews
define_template -type constraint \
-index_1 {0.025 0.1 0.25} \
-index_2 {0.025 0.1 0.25} \
constraint_3x3
# Specify the PVT for this characterization run
set_operating_condition -voltage 1.0 -temp 25

set_var extsim_cmd "spectre"
set_var extsim_deck_header "simulator lang=spectre
ahdl_include 'res_route/veriloga/veriloga.va'
ahdl_include 'negfet_route/veriloga/veriloga.va'
simulator lang=spice\n"

define_leafcell -extsim_model -type nmos -element negfet_route
define_leafcell -extsim_model -type r -element res_route

# Read in the SPICE subckts and models
read_spice -format spectre {Iinput.scs}
# Define how to characterize each group of cells
define_cell \
-input {A} \
-output {Y} \
-delay delay_3x3 \
-power power_3x3 \
-constraint constraint_3x3 \
{INV_X1}
# Perform characterization and write out the library
char_library -ecsm -ccsn -ccsp -extsim spectre -cells {INV_X1} -thread 1

write_library Standard_Library.lib

;;;;END Char script

When I execute this script then liberate gives me error:

Code:

*Error* (char_library) : Failed to find cell 'negfet_route' for instance 'I0' in netlist/model file.
ERROR (LIB-203): (char_library): Cell 'INV_X1' is scheduled for characterization but has no netlist, has an empty subckt or has no port on the subckt. This cell will be skipped. Check the netlist and rerun.

I believe that it couldn't understand the verilog-A model or it is not supported. I tried to include the model using extsim_model_include command but it doesn't work either. Can anyone guide me how can I characterize my cells ?.

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