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Number of Clock Cycles vs Clock period tradeoff

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kaushikrvs

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How does reducing number of clock cycles per instruction might increase the period of clock cycle? Can anyone please provide a clarity for this tradeoff?

I found this while reading the book Computer organization and design, RISC V edition, In the section 1.6 perfomance
 

kaushikrvs said:
How does reducing number of clock cycles per instruction might increase the period of clock cycle? Can anyone please provide a clarity for this tradeoff?

I found this while reading the book Computer organization and design, RISC V edition, In the section 1.6 perfomance
Click to expand...

Pipelining. Simple concept.
 

Thanks for the reply. After trying to understand, I am still not convinced how does it result in increase of a clock cycle, Pipelining means that Fetch and Excute of instructions happen in parallel in the same clock cycle. Why do we need to increase clock period for that ?
 

Huh?

It's the opposite. Pipelining means doing less per clock cycle per instruction which means a faster clock rate (shorter period).
 

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