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No idea what you are talking about... context?
We don't know what is "dsync"!
Please frame your question properly with a proper background explanation or reference (if needed).
back to back flops (synchronizer) on clk1 with async input at d pin. When async input changes, you may see output change after 2-3 clks. Is this correct?
back to back flops (synchronizer)
Why don't you sketch a timing diagram?