smsskil
Newbie level 3
is it possible to encrypt verilog code but can be synthesized in cadence? I need to give my design to customer for his integrating. But I don't know how can i protect my file
Any help?
Any help?
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Hi jbeniston,Yes - but basically you need to encrypt it once each for Cadence / Synopsys / Mentor. Search for 'pragma protect'
Possible as far as you use Cadence Tools in all stage s of design.is it possible to encrypt verilog code but can be synthesized in cadence?