sky_above
Member level 2
When a Dflipflop RTL is written we never assign the Qbar ouput of the flipflop. How does the synthesis tool then choose a Dflipflop cell which has a Qbar output also from the library?
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The logic after the flop may required the inverted value, and so the Qbar is used instead to reduce the logic count.
do you already translate your RTL code in logic gate?
do you see some optimization by removing two consecutives inverter?
always @(posedge clk)
q <= ~q;
dff ff1 (.q(q), .d(d), .c(clk));
inv inv1 (.o(d), .i(q));
dff ff1 (.q(), .q_bar(q_bar) .d(q_bar), .c(clk));