ranaya
Advanced Member level 4
Hi
I am using Cadence Liberate for standard cell characterization (tsmc 40nm). I am not certain about the values we should put into the delay and power templates of the tcl script. I can see that they are given with respect to the slew values against finite capacitive loads of the gate. So in the first place, how do we determine the slew and load value combinations for a given cell to complete the template ?
One paper has defined that, the mean (or central index of load indices) capcitive load should be the corresponding FO4 load of the gate. So if we characterize an inverter cell, this is 4x the input capacitance of the inverter. Then the central index of slew values is essentially the slew observed for the FO4 load. The other indices are halved to the left of the mean and doubled to the right of the mean. Does this sound reasonable ?
Thanks in advance
Anuradha
I am using Cadence Liberate for standard cell characterization (tsmc 40nm). I am not certain about the values we should put into the delay and power templates of the tcl script. I can see that they are given with respect to the slew values against finite capacitive loads of the gate. So in the first place, how do we determine the slew and load value combinations for a given cell to complete the template ?
One paper has defined that, the mean (or central index of load indices) capcitive load should be the corresponding FO4 load of the gate. So if we characterize an inverter cell, this is 4x the input capacitance of the inverter. Then the central index of slew values is essentially the slew observed for the FO4 load. The other indices are halved to the left of the mean and doubled to the right of the mean. Does this sound reasonable ?
Thanks in advance
Anuradha