NikosTS
Advanced Member level 4
Hello,
Im facing the following problem when trying to automatically place and route my design.
Firstly , i implemented my core design and extracted the netlist after CTS, place and route through saveNetlist command in Cadence Encounter.
After that , i create another verilog file where i instantiate the above said module as well as some custom made level shifters ( core + level shifters = top level ).
In order to implement the top level, i synthesize the verilog code and import the design in Encounter.
What is the flow I am supposed to follow?
Until now , i have tried to create 3 power domains : The first one that contains the core design with low voltage ( e.g 1V ) surrounded by 2 block rings ( VDD and VEE), the second one that contains High-to-low voltage level shifters that is surrounded by 3 block rings ( VCC=high voltage, VDD=low voltage , VEE ) and the default domain that contains the low-to-high voltage level shifter . The floorplan area is also surrounded by 3 core rings ( VCC,VDD and VEE ).
I am facing problems especially with special routing : a ) if the power domains do not cover their respective block rings, special routing nets do not extend to the rings, so no connections are made.
b) Because of the 2 different power domains ( VCC=1.8V, VDD=1V ), special routing shorts some internal cell nets although i have added routing blockage .
The custom level shifters were created in Virtuoso, routing blockage layers were used with respect to the layers in internal nets and then the LEF file was exported. I was careful to make the height of the cell an integer multiple ( x2 ) of the standard cell row.
Any ideas/guidance as to how i must proceed? Should i include the custom made shifters as level shifters in .cpf file? How about the power domains? Is this the correct way to deal with this kind of implementation?
Any help would be greatly appreciated as i have wasted very long time to try to figure this out. Feel free to ask for clarifications
Thank you in advance
Im facing the following problem when trying to automatically place and route my design.
Firstly , i implemented my core design and extracted the netlist after CTS, place and route through saveNetlist command in Cadence Encounter.
After that , i create another verilog file where i instantiate the above said module as well as some custom made level shifters ( core + level shifters = top level ).
In order to implement the top level, i synthesize the verilog code and import the design in Encounter.
What is the flow I am supposed to follow?
Until now , i have tried to create 3 power domains : The first one that contains the core design with low voltage ( e.g 1V ) surrounded by 2 block rings ( VDD and VEE), the second one that contains High-to-low voltage level shifters that is surrounded by 3 block rings ( VCC=high voltage, VDD=low voltage , VEE ) and the default domain that contains the low-to-high voltage level shifter . The floorplan area is also surrounded by 3 core rings ( VCC,VDD and VEE ).
I am facing problems especially with special routing : a ) if the power domains do not cover their respective block rings, special routing nets do not extend to the rings, so no connections are made.
b) Because of the 2 different power domains ( VCC=1.8V, VDD=1V ), special routing shorts some internal cell nets although i have added routing blockage .
The custom level shifters were created in Virtuoso, routing blockage layers were used with respect to the layers in internal nets and then the LEF file was exported. I was careful to make the height of the cell an integer multiple ( x2 ) of the standard cell row.
Any ideas/guidance as to how i must proceed? Should i include the custom made shifters as level shifters in .cpf file? How about the power domains? Is this the correct way to deal with this kind of implementation?
Any help would be greatly appreciated as i have wasted very long time to try to figure this out. Feel free to ask for clarifications
Thank you in advance