Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

LDO-pass-transistor-layout floorplan

Status
Not open for further replies.
E

ejcmos

Newbie level 3
Joined
Sep 26, 2014
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
44
LDO pass transistor layout floorplan

Hi all,

I am designing a LDO as second power for a loading block.
The pass transistor is very large for supplying high current.
and also the loading block is very wide.

For the layout floorplan,
Should I distribute the pass transistor to surround the loading block to reduce the IR drop and the feedback line is very long, or concentrate the pass transistor in one place and close to LDO block and also enlarge the power line.
What's the consideration ?

Thank you in advance.
 

Re: LDO pass transistor layout floorplan

Are you allowed to place circuit under pad in this
technology? That's a good place for it (esp. under
output pad). Or between input and output pads
(if there is an output pad, which for transient steps
you might want, for bulk decoupling).

If a PMOS pass FET, do you benefit (stability) or
lose (I*R) from source resistance, inductance? The
best approach is to model parasitics and do a good
what-if analysis based on realities. "Large" is not
a number that tells you what works and what fits,
best.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top