+ Post New Thread
Results 1 to 9 of 9
  1. #1
    Junior Member level 1
    Points: 101, Level: 1

    Join Date
    Mar 2018
    Posts
    17
    Helped
    0 / 0
    Points
    101
    Level
    1

    Simulating Xilinx smpte sdi core

    Hi everyone,

    I have generated this core in Xilinx Vivado. It has a demo tb....

    Can anyone guide me how to simulate it??Can't figure out what files to compile(design files).


    Many thanks

    •   AltAdvertisment

        
       

  2. #2
    Advanced Member level 5
    Points: 36,169, Level: 46
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,614
    Helped
    1927 / 1927
    Points
    36,169
    Level
    46

    Re: Simulating Xilinx smpte sdi core

    Usually the documentation contains information on an IP testbench - the newest document certainly does:

    https://www.xilinx.com/support/docum...-smpte-sdi.pdf


    1 members found this post helpful.

  3. #3
    Advanced Member level 4
    Points: 7,495, Level: 20
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    1,102
    Helped
    244 / 244
    Points
    7,495
    Level
    20
    Blog Entries
    1

    Re: Simulating Xilinx smpte sdi core

    Read Chapter9 of the docu mentioned in the above post.

    1st and foremost, did you generate the core successfully?

    If yes, just right_click inside Vivado on the core top_level file and generate its "example_design".
    Vivado will create a new project for you with a test_bench wrapper over the core.
    Then open this new project and just "Run Simulation".

    Recommended reading : https://www.xilinx.com/support/docum...n-tutorial.pdf
    .....yes, I do this for fun!


    1 members found this post helpful.

    •   AltAdvertisment

        
       

  4. #4
    Junior Member level 1
    Points: 101, Level: 1

    Join Date
    Mar 2018
    Posts
    17
    Helped
    0 / 0
    Points
    101
    Level
    1

    Re: Simulating Xilinx smpte sdi core

    Thanks very much for all your help. This was exactly what I needed

    - - - Updated - - -

    Hi Paul

    thanks for your response. I am able to simulate it but not using the way you described and would be interested to replicate that... When I right click (.......xci) file I don't see the option of generating example design.... Please advise.

    Thanks



    •   AltAdvertisment

        
       

  5. #5
    Advanced Member level 4
    Points: 7,495, Level: 20
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    1,102
    Helped
    244 / 244
    Points
    7,495
    Level
    20
    Blog Entries
    1

    Re: Simulating Xilinx smpte sdi core

    Sorry.....I missed this info.

    See Chapter8 of the IP core spec - "No example design is available at the time for the SMPTE SD/HD/3G-SDI 3.0 core"
    So ignore the way of generation I mentioned above.

    But see Chapter9: "A demonstration test bench is provided with the core which enables you to observe core behavior in a typical scenario. This test be nch is generated together with the core in Vivado Design Suite."
    .....yes, I do this for fun!


    1 members found this post helpful.

  6. #6
    Junior Member level 1
    Points: 101, Level: 1

    Join Date
    Mar 2018
    Posts
    17
    Helped
    0 / 0
    Points
    101
    Level
    1

    Re: Simulating Xilinx smpte sdi core

    BTW Thanks for all your help. I was able to simulate in vivado. What do I need to do if I want to simulate in modelsim/questasim. thanks very much

    - - - Updated - - -

    The problem is I don't see the log file (it is not there in sim dir simulation.log is empty) and the messages about testing the video formats. Also it is just running one record and I would appreciate your help as to figure out why and how to run all the records. Many thanks



  7. #7
    Advanced Member level 4
    Points: 7,495, Level: 20
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    1,102
    Helped
    244 / 244
    Points
    7,495
    Level
    20
    Blog Entries
    1

    Re: Simulating Xilinx smpte sdi core

    What do I need to do if I want to simulate in modelsim/questasim.
    The problem is I don't see the log file (it is not there in sim dir simulation.log is empty) and the messages about testing the video formats.
    Ans to both Q can be found inside the docu - UG900 (v2016.4) November 30, 2016
    .....yes, I do this for fun!



  8. #8
    Junior Member level 1
    Points: 101, Level: 1

    Join Date
    Mar 2018
    Posts
    17
    Helped
    0 / 0
    Points
    101
    Level
    1

    Re: Simulating Xilinx smpte sdi core

    Thanks very much. BTW what does this expression mean in verilog

    v <= # DLY line < first_active-1;



    •   AltAdvertisment

        
       

  9. #9
    Advanced Member level 4
    Points: 7,495, Level: 20
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    1,102
    Helped
    244 / 244
    Points
    7,495
    Level
    20
    Blog Entries
    1

    Re: Simulating Xilinx smpte sdi core

    This is completely different to the topic you started.
    A new thread is needed in this case.

    Please read the forum posting rules!
    .....yes, I do this for fun!



--[[ ]]--