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    Techniques to solve metastability issue in VHDL

    Hello,

    I am wondering about reliable technique to solve metastability in VHDL. One way is double sample of data_ready signal using two FF in series. Here is an example.

    Code:
      
     
     if rising_edge(clk) then
        
        -- double sample to avoid metastability
        ready_r     <= data_ready;                    	
        ready_rr    <= ready_r;
        
        -- detect the rising edge of ready signal     	                       
        if ready_r = '1' and ready_rr = '0' then 
    
        end if;
    Are there other methods to solve metastability ?
    Last edited by expertengr; 6th April 2018 at 10:26.

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    Re: Techniques to solve metastability issue in VHDL

    double register is usually find for single bits, but for larger busses this may not be suitable, and some more elaborate buffer may be needed. The easiest to use would be a dual clock FIFO.



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    Re: Techniques to solve metastability issue in VHDL

    The double sampling you have shared works when you are dealing with signals crossing one clock domain and entering into other clock domain.

    And in that too clock to be used in the sampling FF should be of the receiving domain.



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    Re: Techniques to solve metastability issue in VHDL

    Quote Originally Posted by mjuneja View Post
    The double sampling you have shared works when you are dealing with signals crossing one clock domain and entering into other clock domain.

    And in that too clock to be used in the sampling FF should be of the receiving domain.
    It does work, but the more bits you cross at the same time, the greater risk you have of issues. When you have multiple bits crossing a domain, you have no grantee that you will see all bits correct at the same time, because of the difference in routing lengths.

    So for example - imagine a counter on clk domain A:

    000
    001
    010
    011
    100

    Through a simple double register, you may see the following sequence:

    000
    001
    011
    010
    011
    111
    101
    100
    110

    Because more than 1 bit changes in CLK A, CLK B may sample them violating hold times for some, but not all of the bits.

    This is why, if you have a data bus, you really need something other than a double register to guarantee data safety. So usualy you would use a FIFO, but for slow buses you could use some form of handshaking to validate the data.



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    Re: Techniques to solve metastability issue in VHDL

    Thanks TrickyDicky for your reply.

    Kindly explain little more about dual clock FIFO. If I have 8 data_ready signals which last for approximately 10 clock cycles and I need to capture 12 bit data upon the rising edge of each data_ready signal. The data is coming from eight independent sources and is acknowledged by data_ready signal.



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    Re: Techniques to solve metastability issue in VHDL

    Both Xilinx and Altera provide FIFO IP that has dual clocks. I highly suggest you investigate those.



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    Re: Techniques to solve metastability issue in VHDL

    Hi,

    A FIFO is a very good solution, especially for fast data rates.

    If I have 8 data_ready signals which last for approximately 10 clock cycles and I need to capture 12 bit data upon the rising edge of each data_ready signal.
    If so, then you may detect data_ready and you have plenty of time to sample the data in times where you know there is no transition.
    Those data can safely transferred from one clock domain to the other.

    I recommend you to draw a timing diagram.
    Start with
    * data
    * data_ready
    * and the high speed (async) clock.
    ***
    * double buffer the data_ready signal to avoid metastability problems. (using high speed clock)
    * detect the rising edge of data_ready (using high speed clock. The resulting signal is already delayed to the data_transition.
    * use this signal to capture the data (using high speed clock)

    Klaus
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    Re: Techniques to solve metastability issue in VHDL

    You don't "solve metastability" - you design around it...
    I strongly suggest you read this magnificent paper.
    http://www.sunburst-design.com/paper...Boston_CDC.pdf

    It'll cover the above suggested approaches and much more.
    Let it be your bible when it comes to designing in multiple clock domains...

    Good luck.



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    Re: Techniques to solve metastability issue in VHDL

    Quote Originally Posted by expertengr View Post
    Hello,

    I am wondering about reliable technique to solve metastability in VHDL. One way is double sample of data_ready signal using two FF in series. Here is an example.

    Code:
      
     
     if rising_edge(clk) then
        
        -- double sample to avoid metastability
        ready_r     <= data_ready;                    	
        ready_rr    <= ready_r;
        
        -- detect the rising edge of ready signal     	                       
        if ready_r = '1' and ready_rr = '0' then 
    
        end if;
    Are there other methods to solve metastability ?
    Your example is dangerous!

    If you have 2 registers to eliminate metastability, you should not use the signal between the registers. You should have an additional register to detect the edge.
    Your limited example would probably work, but if you extend it with more logic that use the ready_r signal, the design can fail.

    Never use the signal between the syncronization registers!



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    Re: Techniques to solve metastability issue in VHDL

    I have 8 data_ready signals which last for approximately 10 clock cycles and I need to capture 12 bit data upon the rising edge of each data_ready signal. The data is coming from eight independent sources and is acknowledged by data_ready signal.

    In FIFO solution do I need to store the data in FIFO upon rising edge of clock using a single register instead of double registers ?



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    Re: Techniques to solve metastability issue in VHDL

    When using a FIFO - registers aren't required.
    Simply write on one side and read from the other.



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    Re: Techniques to solve metastability issue in VHDL

    Hi,

    For every input signal to a PLD that is asynchron to the PLD's master clock you should take care about metastability.
    This often is done with the two DFF in series.

    But even if you take care about metastability this doesn't mean that the data is valid.
    For this you need to take your data_ready signals into account.

    To me it's not clear how the 8 data_ready signals are related to 12 data signals.
    Are this 20 lines in total?

    How do you want to process the data?
    In 8 different groups?
    Or combined all 12 signals?

    Is the timing of the 8 data_ready signals absolutely independent?

    Klaus
    Please donīt contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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    Re: Techniques to solve metastability issue in VHDL

    When using a FIFO - registers aren't required.
    Simply write on one side and read from the other.
    Of course DC FIFO uses synchronization registers - inside the FIFO module. The solution involves considerable higher resource usage than simple data ready handshaking. It must be used when the speed requirements are less relaxed than specified by the OP.



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    Re: Techniques to solve metastability issue in VHDL

    Quote Originally Posted by std_match View Post
    Your limited example would probably work, but if you extend it with more logic that use the ready_r signal, the design can fail.
    I take that back! It is worse. You have basically reduced it to a one-stage synchronizer, and it is even possible that the edge detection fail to detect a rising edge if you get a "long" metastability that needs a proper 2-stage synchronizer.
    One problem with metastable signals is that they can be detected as '0' one one logic input and '1' on another logic input.
    This means that the output from the first synchronizer stage must only drive one input, which is the input of the next synchronizer stage.

    In your simple example, the "if ready_r = '1' and ready_rr = '0' then" can fail to detect an edge because the signals can go directly from
    ready_r = '0'
    ready_rr = '0'
    to
    ready_r = '1'
    ready_rr = '1'

    This is because the input to ready_rr can see '1' when the "if" logic sees ready_r = '0'.

    Again, never use the signal between the synchronizer stages!



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    Re: Techniques to solve metastability issue in VHDL

    Quote Originally Posted by expertengr View Post
    Hello,

    I am wondering about reliable technique to solve metastability in VHDL. One way is double sample of data_ready signal using two FF in series. Here is an example.

    Code:
      
     
     if rising_edge(clk) then
        
        -- double sample to avoid metastability
        ready_r     <= data_ready;                    	
        ready_rr    <= ready_r;
        
        -- detect the rising edge of ready signal     	                       
        if ready_r = '1' and ready_rr = '0' then 
    
        end if;
    Are there other methods to solve metastability ?

    What is your application?
    Always remember that you are absolutely unique,
    just like everyone else.



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