+ Post New Thread
Results 1 to 5 of 5

13th March 2018, 16:25 #1
 Join Date
 Mar 2018
 Posts
 1
 Helped
 0 / 0
 Points
 16
 Level
 1
VHDL Multiplying by a fraction
Hello,
I am working on an FPGA design where a 20 bit signal is transferred from one component to another component, where a procedure is performed using the 20bit signal. The calculation performed in the procedure is multiplying the 20 bit signal by 0.00034, or 680/2000000, and then placing this value into a signal of the integer type. However this generates a negative slack for the transfer of data between the register of the 20 bit signal in the first component, and the register of the integer signal in the second component. When I look at the data path in the timing report, it seems that the bulk of the delay is due to the calculation performed in the second component. Is there a less time consuming way to perform the calculation? The calculation in the procedure looks like this at the moment:
Code: Calculates distance in centimeters PROCEDURE calculate_distance ( SIGNAL p_counter_data_in : IN std_logic_vector(19 downto 0); SIGNAL p_distance_data_out : OUT integer ) IS BEGIN p_distance_data_out <= to_integer(unsigned(p_counter_data_in) * 680/2000000); END calculate_distance;

13th March 2018, 16:25

13th March 2018, 16:38 #2
 Join Date
 Sep 2013
 Location
 USA
 Posts
 6,686
 Helped
 1604 / 1604
 Points
 29,071
 Level
 41
Re: VHDL Multiplying by a fraction
What frequency?
What technology?
I don't use fractions in my multiplications, so I'm not sure how many bits that will use in synthesis. I normally define any fractions with a parameter (Verilog) with a defined bit width and treat them as scaled integers, I never let the tools decide how many bits. In this case did the tools define it as 32bits?

13th March 2018, 16:38

13th March 2018, 17:58 #3
 Join Date
 Nov 2013
 Location
 Germany
 Posts
 268
 Helped
 27 / 27
 Points
 1,991
 Level
 10

13th March 2018, 17:58

13th March 2018, 20:42 #4
 Join Date
 Jun 2010
 Posts
 6,589
 Helped
 1924 / 1924
 Points
 36,062
 Level
 46
Re: VHDL Multiplying by a fraction
Can you use the microprocessor to do this multiplication part and output the result in integer??
to the OP: Be careful with your operators. If you did (680/2000000) you would get 0, but actually you're getting (unsigned(p_counter_data_in) * 680) / 20000000.
The divide in this circuit is what is failing the timing. You should really convert 680/20000000 to some kind of offset integer, that you can then shift after the operation. This means no divider is needed. Something like this:
p_distance_data_out <= to_integer(unsigned(p_counter_data_in) * ( (680*(2**16)) /2000000) ) / (2**16);
This should ensure the calculation is a simple A*B, rather than the (A*B)/C you had before.
1 members found this post helpful.

13th March 2018, 21:58 #5
 Join Date
 Mar 2005
 Location
 California, USA
 Posts
 4,007
 Helped
 868 / 868
 Points
 20,798
 Level
 35
Re: VHDL Multiplying by a fraction
If you insist upon using nonpoweroftwo division, have you considered using an IP core or DSP block?
+ Post New Thread
Please login