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    DDR to AXI INTERFACE.......

    DDR Memory have 640x400 data. I need to read each 640bits from DDR memory when I get star bit and stored in 640mb internal memory. After getting each 640 bits in a internal memory in need to write this data in to the same DDR with different write location.
    Platform : zync ultrascal+
    Part: xczu9eg-ffvc900-2-i
    Tool :vivado 2016.4
    Am new to this design. kindly provide your support and Which Xilinx AXI IP is good for this project and provide the project flow.

    - - - Updated - - -

    Here AXI READ&WRITE is my part. I need to read 640bit data from input register and write it to 640bits output register.

    •   Alt7th March 2018, 07:35

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    Re: DDR to AXI INTERFACE.......

    Assuming that the Xilinx MIG core will be used as the DDR memory controller core, I would suggest you to go through the MIG example_design provided by Xilinx. It can have native or AXI interface. As you have already mentioned AXI, so generate this core with AXI interface.
    Then follow the waveforms and understand how the DDR is written and read.

    Choose the docs to read from here: https://www.xilinx.com/support/docum...-ddr3-hub.html
    .....yes, I do this for fun!


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    •   Alt7th March 2018, 10:11

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    Re: DDR to AXI INTERFACE.......

    I need Xilinx AXI Master IP name with the data width of 64bit. kindly suggest which Xilinx IP can i use.



    •   Alt12th March 2018, 06:27

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  4. #4
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    Re: DDR to AXI INTERFACE.......

    Name- Xilinx Memory Interface Generator (MIG)

    Please the the documentation for this IP core first *carefully* (will answer most of your questions).
    .....yes, I do this for fun!



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