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  1. #1
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    Unable to get this verilog code to loop the state machine for number of iterations

    The objective is to perform a singular function with at least a hundred iterations. Final goal is to completely make it gate-level. I could not figure that out so I am trying to get regular code to work. But I cannot get this state machine to loop even twice. There are a lot of random commented codes due to testing things out. I need to get a counter/comparator working somehow. Return to state zero and resume the process. Below is the main code and the testbench I am using to try and test it. I can only get the 1st iteration working. But cannot get anything else.


    Please any assistance would be appreciated. Thank you.

    Code:
    //Verilog module for Project
    `timescale 1ns/1ps
    
    module Project1(
        clk, rst, start,
    	 x_in, u_in, y_in,
    	 x_out, u_out, y_out
      );
    
    //List the inputs and their sizes
    	input clk, rst, start;
    	input [7:0] x_in, u_in, y_in;
    
    //List the outputs and their sizes 
       output integer x_out, u_out, y_out;
    
    //Internal variables
    //	integer  [7:0] rx4, rx2, rdx, r3, rudx, r3ux4_yx4, rux4_x4y;
    //	integer  [7:0] ru_y;
    	reg [7:0] min1, min2; 
    	reg [15:0] tempmult;
    	reg [7:0] ain1, ain2;
    	reg [8:0] tempadd;
    	
    	integer 	x_i, u_i, y_i;
    	integer  rx4, rx2, rdx, r3, rudx, r3ux4_yx4, rux4_x4y;
    	integer  ru_y;
    	integer count = 0;
    //List of Wires
    	
    	
    // Declare state register and parameter
    
    	reg [3:0] state;
    	parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5, S6 = 6;
    	
    //Instantiate Modules ----------------------------------------------------
    
    //Multiplier
    	lpmmult multiply(
    	.clock(clk),
    	.dataa(min1),
    	.datab(min2),
    	.result(mout));
    	
    //Adder
    	adders adderss(
    	.clock(clk),
    	.data0x(ain1),
    	.data1x(ain2),
    	.result(aout));
    	
    
    
    //	always block
    	always @ (posedge clk or posedge rst) begin:FSM_ST
    	
    		// Determine the next state
    		if (rst) begin
    			rdx = 1;
    			r3 = 6;
    			x_i <= x_in;
    			u_i <= u_in;
    			y_i <= y_in;
    
    			
    			state <= S0;
    		end else if(start) begin	//End If Start else
    
    		case (state)
    			S0: begin
    				// Multiplying using instantiated module
    //				min1 <= x_i;
    //				min2 <= x_i;
    //				tempmult <= mout;
    //				rx2 <= tempmult[15:8];
    //				// Adding using instantiated module
    //				ain1 <=x_i;
    //				ain1 <=rdx;
    //				tempadd <= aout;
    //				if (tempadd[8] == 1) begin
    //					x_out <= tempadd[8:1];
    //				end else begin
    //					x_out <= tempadd[7:0];
    //				end
    					
    				
    				rx2 <= x_i*x_i; //Multiplying using regular way
    				x_out <= x_i+rdx; //Adding using regular way
    				
    				if (count < 10) begin
    					count = count + 1;
    					state = S1;
    					$display("Time %2d: x_out %1d is %2d", $time, x_out, y_out);
    					#10;
    				end 
    				else begin
    					state <= S1;
    					end
    					end// End State0
    				
    			S1: begin
    				rx4 <= rx2*rx2;
    				ru_y <= u_i+y_i;
    //			Multiplying using instantiated module
    //				min1 <= rx2;
    //				min2 <= rx2;
    //				tempmult <= mout;
    //				rx4 <= tempmult[15:8];
    //				
    //			Adding using instantiated module
    //				ain1 <=u_i;
    //				ain1 <=y_i;
    //				tempadd <= aout;
    //				if (tempadd[8] == 1) begin
    //					ru_y <= tempadd[8:1];
    //				end else begin
    //					ru_y <= tempadd[7:0];
    //				end
    				
    					state <= S2;
    					end// End State1
    					
    			S2: begin
    				rux4_x4y <= rx4*ru_y;
    				
    //				min1 <= rx4;
    //				min2 <= ru_y;
    //				tempmult <= mout;
    //				rux4_x4y <= tempmult[15:8];
    					state <= S3;
    					end// End State2
    					
    			S3: begin
    				r3ux4_yx4 <= rux4_x4y*r3;
    				
    //				min1 <= rux4_x4y;
    //				min2 <= r3;
    //				tempmult <= mout;
    //				r3ux4_yx4 <= tempmult[15:8];
    				
    					state <= S4;
    					end// End State3
    					
    			S4: begin
    				rudx <= u_i*rdx;
    				u_out <= r3ux4_yx4+u_i;
    				
    //				min1 <= u_i;
    //				min2 <= rdx;
    //				tempmult <= mout;
    //				rudx <= tempmult[15:8];
    //				
    //				// Adding using instantiated module
    //				ain1 <=r3ux4_yx4;
    //				ain1 <=u_i;
    //				tempadd <= aout;
    //				if (tempadd[8] == 1) begin
    //					u_out <= tempadd[8:1];
    //				end else begin
    //					u_out <= tempadd[7:0];
    //				end
    					state <= S5;
    					end// End State4
    					
    			S5: begin
    				y_out <= rudx + y_i;
    				
    // 			Adding using instantiated module
    //				ain1 <=rudx;
    //				ain1 <=y_i;
    //				tempadd <= aout;
    //				if (tempadd[8] == 1) begin
    //					y_out <= tempadd[8:1];
    //				end else begin
    //					y_out <= tempadd[7:0];
    //				end
    
    					state <= S6;
    					end// End State5
    					
    			S6: begin
    
    				//Write output code Here
    				if (start) begin
    					state = S0;
    				
    				end
    //				if (count < 10) begin
    //					count = count + 1;
    //					state = S0;
    //					$display("Time %2d: x_out %1d is %2d", $time, x_out, y_out);
    //					#10;
    //				end 
    					
    				end// End State6
    			default:
    				state <= S6;
    				
    			endcase
    			
    		end // End Else
    
    
    	
    	end// End always module
    	
    //	always @ (posedge clk) begin:FSM_S
    //				if (count < 10) begin
    //					count = count + 1;
    //					//state = S0;
    //					$display("Time %2d: x_out %1d is %2d", $time, x_out, y_out);
    //					#10;
    //				end 
    //	end
    
    endmodule






    Code:
    //Verilog testbench module for Project
    `timescale 1ns/1ps
    
    module Project1_tb;
    
      reg clk, rst, start; //reset = active HIGH
    
      integer  x_in, u_in, y_in;
      wire [7:0] x_out, u_out, y_out;
      
      Project1 uut(
    
        .clk(clk), .rst(rst), .start(start),
    	 .x_in(x_in), .u_in(u_in), .y_in(y_in),
    	 .x_out(x_out), .u_out(u_out), .y_out(y_out)
      );
      
    	initial begin   
    		clk = 0;  
    		forever #50 clk = ~clk;  
    	end 
    
    	initial begin
    		#1000;
    		start = 0;
    		x_in = 8'b00000010;
    		u_in = 8'b00000100;
    		y_in = 8'b00000100;
    		rst = 1;
    		#1000;
    		rst = 0;
    		#1000;
    		start = 1;
    		#1000; 
    		start = 0;
    		#1000;
    		rst = 1;
    		#1000;
    		rst = 0;
    		#1000;
    		start = 1;
    		#50000;
    	end
    
    endmodule

    •   Alt5th March 2018, 00:31

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  2. #2
    Advanced Member level 4
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    Re: Unable to get this verilog code to loop the state machine for number of iteration

    Quote Originally Posted by GurenMarkV View Post
    The objective is to perform a singular function with at least a hundred iterations. Final goal is to completely make it gate-level. I could not figure that out so I am trying to get regular code to work. But I cannot get this state machine to loop even twice. There are a lot of random commented codes due to testing things out. I need to get a counter/comparator working somehow. Return to state zero and resume the process. Below is the main code and the testbench I am using to try and test it. I can only get the 1st iteration working. But cannot get anything else.


    Please any assistance would be appreciated. Thank you.

    Code:
    //Verilog module for Project
    `timescale 1ns/1ps
    
    module Project1(
        clk, rst, start,
    	 x_in, u_in, y_in,
    	 x_out, u_out, y_out
      );
    
    //List the inputs and their sizes
    	input clk, rst, start;
    	input [7:0] x_in, u_in, y_in;
    
    //List the outputs and their sizes 
       output integer x_out, u_out, y_out;
    
    //Internal variables
    //	integer  [7:0] rx4, rx2, rdx, r3, rudx, r3ux4_yx4, rux4_x4y;
    //	integer  [7:0] ru_y;
    	reg [7:0] min1, min2; 
    	reg [15:0] tempmult;
    	reg [7:0] ain1, ain2;
    	reg [8:0] tempadd;
    	
    	integer 	x_i, u_i, y_i;
    	integer  rx4, rx2, rdx, r3, rudx, r3ux4_yx4, rux4_x4y;
    	integer  ru_y;
    	integer count = 0;
    //List of Wires
    	
    	
    // Declare state register and parameter
    
    	reg [3:0] state;
    	parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5, S6 = 6;
    	
    //Instantiate Modules ----------------------------------------------------
    
    //Multiplier
    	lpmmult multiply(
    	.clock(clk),
    	.dataa(min1),
    	.datab(min2),
    	.result(mout));
    	
    //Adder
    	adders adderss(
    	.clock(clk),
    	.data0x(ain1),
    	.data1x(ain2),
    	.result(aout));
    	
    
    
    //	always block
    	always @ (posedge clk or posedge rst) begin:FSM_ST
    	
    		// Determine the next state
    		if (rst) begin
    			rdx = 1;
    			r3 = 6;
    			x_i <= x_in;
    			u_i <= u_in;
    			y_i <= y_in;
    
    			
    			state <= S0;
    		end else if(start) begin	//End If Start else
    
    		case (state)
    			S0: begin
    				// Multiplying using instantiated module
    //				min1 <= x_i;
    //				min2 <= x_i;
    //				tempmult <= mout;
    //				rx2 <= tempmult[15:8];
    //				// Adding using instantiated module
    //				ain1 <=x_i;
    //				ain1 <=rdx;
    //				tempadd <= aout;
    //				if (tempadd[8] == 1) begin
    //					x_out <= tempadd[8:1];
    //				end else begin
    //					x_out <= tempadd[7:0];
    //				end
    					
    				
    				rx2 <= x_i*x_i; //Multiplying using regular way
    				x_out <= x_i+rdx; //Adding using regular way
    				
    				if (count < 10) begin
    					count = count + 1;
    					state = S1;
    					$display("Time %2d: x_out %1d is %2d", $time, x_out, y_out);
    					#10;
    				end 
    				else begin
    					state <= S1;
    					end
    					end// End State0
    				
    			S1: begin
    				rx4 <= rx2*rx2;
    				ru_y <= u_i+y_i;
    //			Multiplying using instantiated module
    //				min1 <= rx2;
    //				min2 <= rx2;
    //				tempmult <= mout;
    //				rx4 <= tempmult[15:8];
    //				
    //			Adding using instantiated module
    //				ain1 <=u_i;
    //				ain1 <=y_i;
    //				tempadd <= aout;
    //				if (tempadd[8] == 1) begin
    //					ru_y <= tempadd[8:1];
    //				end else begin
    //					ru_y <= tempadd[7:0];
    //				end
    				
    					state <= S2;
    					end// End State1
    					
    			S2: begin
    				rux4_x4y <= rx4*ru_y;
    				
    //				min1 <= rx4;
    //				min2 <= ru_y;
    //				tempmult <= mout;
    //				rux4_x4y <= tempmult[15:8];
    					state <= S3;
    					end// End State2
    					
    			S3: begin
    				r3ux4_yx4 <= rux4_x4y*r3;
    				
    //				min1 <= rux4_x4y;
    //				min2 <= r3;
    //				tempmult <= mout;
    //				r3ux4_yx4 <= tempmult[15:8];
    				
    					state <= S4;
    					end// End State3
    					
    			S4: begin
    				rudx <= u_i*rdx;
    				u_out <= r3ux4_yx4+u_i;
    				
    //				min1 <= u_i;
    //				min2 <= rdx;
    //				tempmult <= mout;
    //				rudx <= tempmult[15:8];
    //				
    //				// Adding using instantiated module
    //				ain1 <=r3ux4_yx4;
    //				ain1 <=u_i;
    //				tempadd <= aout;
    //				if (tempadd[8] == 1) begin
    //					u_out <= tempadd[8:1];
    //				end else begin
    //					u_out <= tempadd[7:0];
    //				end
    					state <= S5;
    					end// End State4
    					
    			S5: begin
    				y_out <= rudx + y_i;
    				
    // 			Adding using instantiated module
    //				ain1 <=rudx;
    //				ain1 <=y_i;
    //				tempadd <= aout;
    //				if (tempadd[8] == 1) begin
    //					y_out <= tempadd[8:1];
    //				end else begin
    //					y_out <= tempadd[7:0];
    //				end
    
    					state <= S6;
    					end// End State5
    					
    			S6: begin
    
    				//Write output code Here
    				if (start) begin
    					state = S0;
    				
    				end
    //				if (count < 10) begin
    //					count = count + 1;
    //					state = S0;
    //					$display("Time %2d: x_out %1d is %2d", $time, x_out, y_out);
    //					#10;
    //				end 
    					
    				end// End State6
    			default:
    				state <= S6;
    				
    			endcase
    			
    		end // End Else
    
    
    	
    	end// End always module
    	
    //	always @ (posedge clk) begin:FSM_S
    //				if (count < 10) begin
    //					count = count + 1;
    //					//state = S0;
    //					$display("Time %2d: x_out %1d is %2d", $time, x_out, y_out);
    //					#10;
    //				end 
    //	end
    
    endmodule






    Code:
    //Verilog testbench module for Project
    `timescale 1ns/1ps
    
    module Project1_tb;
    
      reg clk, rst, start; //reset = active HIGH
    
      integer  x_in, u_in, y_in;
      wire [7:0] x_out, u_out, y_out;
      
      Project1 uut(
    
        .clk(clk), .rst(rst), .start(start),
    	 .x_in(x_in), .u_in(u_in), .y_in(y_in),
    	 .x_out(x_out), .u_out(u_out), .y_out(y_out)
      );
      
    	initial begin   
    		clk = 0;  
    		forever #50 clk = ~clk;  
    	end 
    
    	initial begin
    		#1000;
    		start = 0;
    		x_in = 8'b00000010;
    		u_in = 8'b00000100;
    		y_in = 8'b00000100;
    		rst = 1;
    		#1000;
    		rst = 0;
    		#1000;
    		start = 1;
    		#1000; 
    		start = 0;
    		#1000;
    		rst = 1;
    		#1000;
    		rst = 0;
    		#1000;
    		start = 1;
    		#50000;
    	end
    
    endmodule
    You have a mix of blocking and non-blocking assignments on the same always block. That is not only bad practice, as it is really hard to debug.
    Really, I am not Sam.



    •   Alt5th March 2018, 04:19

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  3. #3
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    Re: Unable to get this verilog code to loop the state machine for number of iteration

    Quote Originally Posted by ThisIsNotSam View Post
    You have a mix of blocking and non-blocking assignments on the same always block. That is not only bad practice, as it is really hard to debug.

    I do not know what blocking and non-blocking is or how that affects the result since it did compile and give output once. Can you go into a bit more detail?



    •   Alt5th March 2018, 05:14

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  4. #4
    Super Moderator
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    Re: Unable to get this verilog code to loop the state machine for number of iteration

    I do not know what blocking and non-blocking is or how that affects the result
    You should definitely consider to learn about it. Start with the classical Cummings paper http://www.sunburst-design.com/paper...2000SJ_NBA.pdf



  5. #5
    Advanced Member level 4
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    Re: Unable to get this verilog code to loop the state machine for number of iteration

    Quote Originally Posted by GurenMarkV View Post
    I do not know what blocking and non-blocking is or how that affects the result
    Well, there is your homework then :)
    Really, I am not Sam.



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