irrational clk period

1. Re: irrational clk period

Just run the code in post #1 with any simulation time step resolution according to your requirements, e.g. 10 ps, 1 ps, as you like. The time variable is a real type with sufficient resolution, but the actual wait time interval is rounded according to the simulation time step.

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2. Re: irrational clk period

First of all, your basic premise is wrong. You can't have an "irrational" period. That's a purely mathematical concept.

Set your timing resolution to 1 ps.
Set t_high and t_low=6.849 ns.

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3. Re: irrational clk period

Originally Posted by nsgil85
Yes
Sorry but I do not understand why it is difficult to answer my question
because you are asking it wrong.

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4. Re: irrational clk period

You can try this.
Code:
```procedure cgen(signal clk : out std_logic;) is
constant P: time := 13698 ps;
constant HIGH_T : time := P/2;
constant LOW_T  : time := P/2;
begin
loop
clk <= '1';
wait for HIGH_T;
clk <= '0';
wait for LOW_T;
end loop;
end procedure;```
Just a minor modification in your code.
And ensure time resolution of your simulator to be 1ps.

5. Re: irrational clk period

Just a minor modification in your code.
The code in post #1 will achieve the same.

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6. Re: irrational clk period

Originally Posted by FvM
The code in post #1 will achieve the same.
25 posts and we have now circumnavigated the thread.