rafimiet
Member level 5
I have a VHDL code as below
Description: I have a signal b0, which is initialized as some 1's and some 0's. Then it is updated by some other components of the main architecture.
It shows me an error "[Netlist 29-101] Netlist 'b0_decision' is not ideal for floorplanning, since the cellview 'b0_decision' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning."
Also it takes 21050 LUTs and 16381 FFs
Can you make me understand what is being wrong here and how to correct it? Also I need to understand with what logic does it implement it?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 entity b0_decision is GENERIC (N : integer := 256); Port ( b0_addr : in integer range 0 TO N*N/4-1; clk,update : in STD_LOGIC; valid : out STD_LOGIC := '1'); end b0_decision; architecture Behavioral of b0_decision is signal b0 : STD_LOGIC_VECTOR (N*N/4-1 downto 0) := (1 TO 3 => '1', OTHERS => '0'); begin valid <= b0(b0_addr); process(clk) begin if clk'event and clk = '1' then if update = '1' then b0(b0_addr) <= '1'; end if; end if; end process; end Behavioral;
Description: I have a signal b0, which is initialized as some 1's and some 0's. Then it is updated by some other components of the main architecture.
It shows me an error "[Netlist 29-101] Netlist 'b0_decision' is not ideal for floorplanning, since the cellview 'b0_decision' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning."
Also it takes 21050 LUTs and 16381 FFs
Can you make me understand what is being wrong here and how to correct it? Also I need to understand with what logic does it implement it?
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