# Example of a manually mapped problem to FPGA logic block

1. ## Example of a manually mapped problem to FPGA logic block

I am looking for an example which shows a simple circuit that is manually placed (mapped) to an FPGA logic block. Assume Xilinx XC4000 which is a simple one and is thought in some textbooks as an example. The explanations only say about the block itself that it is possible to map sequential and combinational circuits. Moreover, it is not very clear how the logic function is implemented. For example it is stated here (see the text below Figure 1.7) they are based on LUTs. So, why they aren't called LUTs?!

So, has any one seen an example in a book that manually maps a simple problem to a basic logic block?

•

2. ## Re: Example of a manually mapped problem to FPGA logic block

Not quite sure why you would want to?
The examples you give are very old (XC4000 chip is nearly 20 years old!). You would do much better following tutorials provided by the vendors.
What exactly are you looking for and why?

•

3. ## Re: Example of a manually mapped problem to FPGA logic block

placement and mapping are two different problems. I believe you are talking about mapping. There are ways to instantiate the FPGA LUTs directly, to which you can map anything you want. Maybe that is what you want, it's not clear.

•

4. ## Re: Example of a manually mapped problem to FPGA logic block

Yes, my question is about mapping for sure.
Assume, you are going to map a simple 1-bit full adder to a typical CLB no matter if it is new or old. It is easy to design a two 3-input LUTs for sum and carry. But when it comes to commercial products, some names are changed due to different functionalities. What is the interior of function generators (G and F)? If they are more than a simple LUT, what else do they have?!

5. ## Re: Example of a manually mapped problem to FPGA logic block

Originally Posted by mahmood.n
Yes, my question is about mapping for sure.
Assume, you are going to map a simple 1-bit full adder to a typical CLB no matter if it is new or old. It is easy to design a two 3-input LUTs for sum and carry. But when it comes to commercial products, some names are changed due to different functionalities. What is the interior of function generators (G and F)? If they are more than a simple LUT, what else do they have?!
This is old technology, you really should be looking at something more modern, like this:
https://www.xilinx.com/support/docum...Series_CLB.pdf

Now, CLB are mostly just a LUT (6 inputs in this case) with a register and some connection muxes. That is it. This architecture hasnt really changed for 10+ years.
Names havent changed in all the time Ive been programming.

So I still dont see what your question is. We generally dont care too much about the mapping, as with good coding and design style, it will map nicely to the blocks.

--[[ ]]--