samster19
Newbie
Hi,
I am required to design a current DAC (64 unit element NMOS) that sinks the output of another current DAC (16 unit element PMOS). The smallest current output from the PMOS DAC is 6uA and the required step size in current from the NMOS DAC is 6uA/256. I am confused as to how to bias the DAC to sink and output these current numbers, any pointers please? Also, the select bits for the DAC will be synced with a feedback clock as this DAC is meant for fine tuning the frequency of a PLL.
I am required to design a current DAC (64 unit element NMOS) that sinks the output of another current DAC (16 unit element PMOS). The smallest current output from the PMOS DAC is 6uA and the required step size in current from the NMOS DAC is 6uA/256. I am confused as to how to bias the DAC to sink and output these current numbers, any pointers please? Also, the select bits for the DAC will be synced with a feedback clock as this DAC is meant for fine tuning the frequency of a PLL.
