FecP
Newbie level 6
Hi! I am trying to infer a single port ram with width = 8 bits and depth = 2^13.
This is the code that I've pulled from the templates and the altera website for a single port ram with one read/write address and write before read behaviour.
When I compile this, I get the following warning
"Warning (276002): Cannot convert all sets of registers into RAM megafunctions when creating nodes; therefore, the resulting number of registers remaining in design can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis."
Strangely, explicitly using the megafunction wizard/IP core, I get no such warning and I can verify that the exact same ram configuration has been synthesized.
What appears to be the problem?
Thank you!
This is the code that I've pulled from the templates and the altera website for a single port ram with one read/write address and write before read behaviour.
Code:
reg [7:0] ram[8191:0];
reg [12:0] ptr;
reg [12:0] ptr_reg;
always @ (posedge read_clock)
begin
if (we)
ram[ptr] <= Write_Val1;
ptr_reg <= ptr;
end
always @(posedge read_clock)
begin
if (!RESET) ptr <= 0;
else if (we || re) ptr <= ptr + 1;
end
assign outputq = ram[ptr_reg];
When I compile this, I get the following warning
"Warning (276002): Cannot convert all sets of registers into RAM megafunctions when creating nodes; therefore, the resulting number of registers remaining in design can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis."
Strangely, explicitly using the megafunction wizard/IP core, I get no such warning and I can verify that the exact same ram configuration has been synthesized.
What appears to be the problem?
Thank you!