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verilog code for serial in parallel out shift register

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ecasha

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Code Verilog - [expand]
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module trai1enc( din ,clk ,reset ,dout );
output [2:0] dout ;
wire [2:0] dout ;
input [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
reg [2:0]s;
initial s=0;
assign din[0]=1;
assign din[1]=0;
assign din[2]=0;
assign din[3]=1;
genvar i;
for (i=0;i<=3;i=i+1)
begin
if (i==0)begin     //i=0
 always @ (posedge (clk)) begin 
 if (reset)
  s <= 0;
 else begin
   s[2] <= din[0];
   s[1] <= s[2];
   s[0] <= s[1];
 end
end
assign dout = s;
end
else if (i==1)begin  //i=1
 always @ (posedge (clk)) begin 
 if (reset)
  s <= 0;
 else begin
   s[2] <= din[1];
   s[1] <= s[2];
   s[0] <= s[1];
 end
end
assign dout = s;
end
else if (i==2)begin //i=2
 always @ (posedge (clk)) begin 
 if (reset)
  s <= 0;
 else begin
   s[2] <= din[2];
   s[1] <= s[2];
   s[0] <= s[1];
 end
end
assign dout = s;
end
else begin
always @ (posedge (clk)) begin //i=3
 if (reset)
  s <= 0;
 else begin
   s[2] <= din[3];
   s[1] <= s[2];
   s[0] <= s[1];
 end
end
assign dout = s;
end
end
endmodule

I want to give the input in code itself.I dont want to use testbench to give different serial inputs. I n above code i have used for loop but index is not incrementing how to write the code?please suggest me
 
Last edited by a moderator:

I am not checking your code!
I want to give the input in code itself.I don't want to use testbench to give different serial inputs.
Click to expand...
A test-bench is highly recommended. Your design/logic needs to interact with the outside world. The top-level ports are the path-ways for your design/logic to receive and output data.
How do you feed-in or monitor data of your design?
By using a test-bench. Follow proper-design methodology, get into the habit of writing test-benches.
 

You are generating multiple always blocks that are assigning different values to the same reg bits. Causes multiple driver error in synthesis and useless simulation code.
 

The OP looks like they are trying to write a mixture of hardware (always @(posedge clk) begin) and software for loops, it's no wonder they are having problems.

- - - Updated - - -

Shift register code...

Code Verilog - [expand]
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parameter SWIDTH = 16;
reg [SWIDTH-1:0] shift_reg;
always @ (posedge clk) begin
  if (shift) begin
    shift_reg <= {shift_reg[SWIDTH-2:0], serial_in};
  end
end

shift_reg is a 16-bit parallel output.

I haven't shown any code for shift or for determining you've shifted 16-bits of data and now have your parallel output. But as you can see this is NOT written like software. For loops are useless for hardware unless your plan is to replicate something and are too lazy (a good thing in this case) to write multiple instances of something that is very repetitive.
 

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