MrMuffins
Newbie level 1
Although I have completed a university course in digital logic, I am new to VHDL design and I am hoping if someone can help me create 2 clock signals which depend on the state of one another.
I am using a 50 MHz clock on a DE2-115 FPGA board that is used to create a 5MHz clock (named dclk) and a second clock named dload which is triggered after 8 dclk cycles. There is a pause (both clocks are 0) between the 8 dclk cycles and the rising edge of dload and another pause after the falling edge of dload and the start of a new set of 8 dclk cycles. I posted the datasheet with a picture of the two clocks and their requirements.
datasheet of the 2 clocks:
My attempt:
I am using a 50 MHz clock on a DE2-115 FPGA board that is used to create a 5MHz clock (named dclk) and a second clock named dload which is triggered after 8 dclk cycles. There is a pause (both clocks are 0) between the 8 dclk cycles and the rising edge of dload and another pause after the falling edge of dload and the start of a new set of 8 dclk cycles. I posted the datasheet with a picture of the two clocks and their requirements.
datasheet of the 2 clocks:
My attempt:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity comp_dclk is
generic(
dclk_interval : integer := 20
);
port(
clk : in std_logic; --reference clock, which is 50MHz
start : in std_logic; --dload starts dclk
dclk : out std_logic; --desired dclk, 50MHz/20 = 2.5MHz, 20 clk cycles = 1 dclk cycle
dload : out std_logic
);
end comp_dclk;
architecture behaviour of comp_dclk is
signal counter : integer range 0 to dclk_interval := 0;
signal dclk_counter : integer range 0 to 8 := 0;
signal start_dclk : std_logic := '0';
signal dclk_done_flg : std_logic := '1';
begin
--0.4 us per dclk cycle
--0.4*7+0.2 = 3us
--8 dclk cycles last 3us
--
--dload period constraint: min 1.55us
--actual dload period: 3us + 35ms
--dload pulse width: min 30ns +5 tol (*)
--dload falling edge to 1st dclk delay: min 45ns +5 tol (**)
--dload stays low and dclk cycles for : 3us
--dclk to dload delay: min 35ns +5 tol (***)
dload_proc : process
begin
if(dclk_done_flg = '1') then --when 8 cycles of dclk is done in dclk_proc, dload process begins
dclk_done_flg <= '0'; --resets dclk flag
wait for 40 ns; --(***)pause required for ink cartridge
dload <= '1'; --dload is 1
wait for 35 ns; --(*)dload is 1 for 35ns
dload <= '0';
wait for 50 ns; --(**)pause required for ink cartridge
start_dclk<='1';
end if;
end process dload_proc;
dclk_proc : process(clk)
begin
if(clk'event and clk='1' and start_dclk='1') then
counter <= counter + 1;
if(counter = dclk_interval) then --if counter is 20, reset to 0. End of a single dclk cycle
counter <= 0;
dclk_counter <= dclk_counter + 1; --counts 8 dclk cycles to begin or end dload signal
end if;
if(counter < dclk_interval/2) then --dclk
dclk <= '1'; --if counter is between and including 0 and 9, state is high
else --if counter is between and including 10 and 19, state is low
dclk <= '0';
end if;
if(dclk_counter = 8) then
start_dclk <= '0';
dclk_done_flg <= '1'; --dload_proc is initiated
counter <= 0;
dclk_counter <= 0;
end if;
end if;
end process dclk_proc;
end architecture behaviour;
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