Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

DSP48E1 - Warning: OPMODE Input Warning

Status
Not open for further replies.
FuzzySNR

FuzzySNR

Member level 2
Joined
Oct 3, 2005
Messages
47
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,688
I get the following warning during co-simulation of my design in Vivado HLS 2016.4:

Code: 
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 138265 ns  Iteration: 11  Process: /apatb_triangulate2D_top/AESL_inst_triangulate2D/grp_insertSite_fu_72/grp_legalizeEdge_fu_336/grp_inCircle_fu_1093/grp_triArea_fu_92/triangulate2D_fsubkb_U1/triangulate2D_ap_fsub_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/Xilinx/Vivado/2016.4/data/vhdl/src/unisims/primitive/DSP48E1.vhd

The simulation seems to stuck at iteration 11-12 forever. Quick look at DSP48E1.vhd source tells me that OPMODE input probably takes some initialized values that DSP48E1 complains about.

Anyone else suffering the same warning? Any ideas how to fix that?
 

You can instantiate the DSP48E1 manually. This can be quite laborious tough, and will restrict the portability (can be ported only to others devices who has DSP48E1).

Can you share the part of the code that uses the DSP48E1?
 

No unfortunately not, the user edited rtl code generated from the high level synthseis tool goes that deep in the hierarchy as of the translated c functions of the user code.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top