msdarvishi
Full Member level 4
Hello,
Here is a snapshot of my fully routed and implemented into the FPGA. I use Vivado Design Suite 2016.1. Previously, when using FPGA_Editor in ISE, we could extract the net delay of each routed wire by clicking on it and then push the"delay" button or using the delay command in Tcl command line to see the net demay of this wire.
I am going to do the same procedure in Vivado for the selected net (white in the picture), but I cannot ! I saw a command named get_net_delays -of_objects, but it does not work here !!
P.S. my route's name is xOutStepReg_reg_n_105 located in the following tree map of Netlist :
arnd2/Nets/ct6/Nets/xOutStepReg_reg_n_105
Kind helps are in advance appreciated.
Thanks,
Here is a snapshot of my fully routed and implemented into the FPGA. I use Vivado Design Suite 2016.1. Previously, when using FPGA_Editor in ISE, we could extract the net delay of each routed wire by clicking on it and then push the"delay" button or using the delay command in Tcl command line to see the net demay of this wire.
I am going to do the same procedure in Vivado for the selected net (white in the picture), but I cannot ! I saw a command named get_net_delays -of_objects, but it does not work here !!
P.S. my route's name is xOutStepReg_reg_n_105 located in the following tree map of Netlist :
arnd2/Nets/ct6/Nets/xOutStepReg_reg_n_105
Kind helps are in advance appreciated.
Thanks,
